Scanning-line drive circuit
AssigneeMitsubishi Electric Corporation
InventorYouichi Tobita
Life of this patent
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Abstract
A gate-line drive circuit is driven by three clock signals of different phases, and includes a plurality of cascade-connected unit shift registers. In a normal operation, activation periods of the three clock signals do not overlap one another. However, the two clock signals of them are simultaneously activated at the beginning of a frame period. A unit shift register of the first stage is adapted to activate an output signal in accordance with the simultaneous activation of the two clock signals.
Claims9
A scanning-line drive circuit driven by using at least two clock signals of different phases, and including a plurality of cascade-connected unit shift registers, wherein
- said scanning-line drive circuit is operable to perform a forward-direction shift for shifting a signal from an immediately preceding stage toward a subsequent stage and a reverse-direction shift for shifting a signal from a subsequent stage toward a immediately preceding stage in said plurality of unit shift registers,
- said scanning-line drive circuit comprises:
- a voltage signal generator;
- a clock signal generator;
- a first voltage signal terminal to which supplied is a first voltage signal set by the voltage signal generator which is set at an activation level at a time of the forward-direction shift and at a deactivation level at a time of the reverse-direction shift;
- and
- a second voltage signal terminal to which supplied is a second voltage signal set by the voltage signal generator which is set at an activation level at a time of the reverse-direction shift and at a deactivation level at a time of the forward-direction shift,
- said plurality of unit shift registers include:
- a first unit shift register which activates an output signal when said first and second voltage signals are both set at an activation level at a time of the forward-direction shift;
- and
- a second unit shift register which activates an output signal when said first and second voltage signals are both set at the activation level at a time of the reverse-direction shift,
- wherein the first and second voltage signals are separate from a connection to a low-side power supply potential, VSS, a connection to a high-side power supply potential, VDD, and any output signals that are output from other unit shift registers, that are applied to each of the unit shift registers,
- wherein at a time of the forward-direction shift, said first and second voltage signals are both set at the activation level at a timing corresponding to the beginning of each frame period based on a clock signal generated by the clock signal generator;
- and
- wherein also at a time of the reverse-direction shift, said first and second voltage signals are both set at the activation level at a timing corresponding to the beginning of each frame period based on a clock signal generated by the clock signal generator.
Dependencies are inferred from the claim text.