# US 10,762,853 B2 · Gate driving circuit and electroluminescent display using the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,762,853 B2 - Document ID: US10762853B2 - Status: Granted - Kind: B2 - Application number: 16/050,129 - Filed: 2018-07-31 - Published: 2019-02-28 - Granted: 2020-09-01 - Earliest claimed: 2017-08-31 - Assignees: LG Display Co., Ltd. - Applicants: LG Display Co., Ltd. - Inventors: Chungsik Kong; Honggyu Han; Mihee Shin; Sewan Lee - Web page: https://patentgrep.com/patent/US10762853B2 ## CPC - G09G 3/3291: in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements - G09G 3/3266: Details of drivers for scan electrodes - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G11C 19/287: {Organisation of a multiplicity of shift registers} - G09G 3/3677: {suitable for active matrices only} - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2300/0426: Layout of electrodes and connections - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An organic light emitting display comprises pixels connected to gate lines, and a gate driving circuit to supply a gate signal to at least one gate line, and having stages connected to each other in a cascading way. A nth (n is a positive integer) stage of the gate driving circuit includes a Q1 node charging unit to charge a Q1 node to a turn-on voltage using first and second clock signals in reverse-phase, and a pull-up transistor to apply the turn-on voltage to an output terminal in response to a Q1 node voltage. The Q1 node charging unit includes a first charging unit to charge the Q1 node voltage to the turn-on voltage using the second clock signal; and a second charging unit to charge a Q2 node, coupled to the Q1 node, using the first clock signal in a section where the Q1 node has the turn-on voltage. ## Claims ### Claim 1 An electroluminescent display comprising: pixels connected to gate lines; and a gate driving circuit to supply a gate signal to at least one of the gate lines, and composed of a plurality of stages connected to each other in a cascading way, wherein an nth (n is a positive integer) stage of the gate driving circuit comprises: a Q1 node charging unit to charge a Q1 node to a turn-on voltage using a first and a second clock signal, a pull-up transistor to apply a turn-on voltage to an output terminal in response to a voltage of the Q1 node, a pull-down unit to control the output terminal to output a turn-off voltage in response to a voltage of a QB1 node; and a node controller to control the voltage of the QB1 node to a level opposite to a level of the voltage of the Q1 node, wherein the Q1 node charging unit comprises: a first charging unit to charge the voltage of the Q1 node to a turn-on voltage using the second clock signal, and a second charging unit to charge a Q2 node, coupled to the Q1 node, using the first clock signal in a section where the Q1 node has a turn-on voltage, wherein the node controller comprises: a QB2 node controller to apply a turn-on voltage of the first clock signal to a QB2 node in response to a voltage of a QP node, and wherein the QB2 node controller further comprises: a second capacitor connected between the QP node and the QB2 node; and a QP node controller connected between a QB2 node of a (n-1)th stage and the QP node. ### Claim 2 (depends on 1) The electroluminescent display of claim 1, wherein the first charging unit comprises a first transistor connected between a start signal input terminal and the Q1 node and having a gate electrode connected to an input terminal of the second clock signal, wherein the second charging unit comprises a second transistor connected between an input terminal of the first clock signal and the Q2 node and having a gate electrode connected to the Q1 node, and a first capacitor connected between the Q1 node and the Q2 node. ### Claim 3 (depends on 1) The electroluminescent display of claim 1, wherein the node controller further comprises a QB1 node controller connected to an input terminal of the first clock signal, from which a gate electrode is applied with the first clock signal, and to apply a voltage of the QB2 node to the QB1 node. ### Claim 4 (depends on 1) The electroluminescent display of claim 1, wherein the first and second clock signals are in reverse-phase. ### Claim 5 (depends on 1) The electroluminescent display of claim 1, wherein one cycle of each of the first and the second clock signals is two horizontal periods. ### Claim 6 An electroluminescent display comprising: pixels connected to gate lines; and a gate driving circuit to supply a gate signal to at least one of the gate lines, and composed of a plurality of stages connected to each other in a cascading way, wherein an nth (n is a positive integer) stage of the gate driving circuit comprises: a Q1 node charging unit to charge a Q1 node to a turn-on voltage using a first and a second clock signal, a pull-up transistor to apply a turn-on voltage to an output terminal in response to a voltage of the Q1 node, a pull-down unit to control the output terminal to output a turn-off voltage in response to a voltage of a QB1 node; and a node controller to control the voltage of the QB1 node to a level opposite to a level of the voltage of the Q1 node, wherein the pull-down unit is configured as double buffers, wherein the double buffers comprises two transistors, and the two transistors comprise gate electrodes connected to different nodes and output the turn-off voltage. ### Claim 7 (depends on 6) The electroluminescent display of claim 6, wherein the pull-down unit comprises: a first pull-down transistor operates in response to an electric potential of the QB1 node; and a second pull-down transistor operates in response to the electric potential of a QB2 node.