Signal supply circuit and display device
AssigneeJapan Display Inc.
InventorsTakayuki Nakao, Takehiro Shima
Life of this patent
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Abstract
According to an embodiment, in a display device, pixels have memories respectively. A signal supply circuit includes a mode control circuit, and switches into a first mode or a second mode to supply digital data pieces to sub-pixels. In the first mode, the circuit receives from the outside first video data pieces corresponding to n sub-pixels, and supplies digital data pieces for the n sub-pixels to corresponding memories. In the second mode, the signal supply circuit receives from the outside second video data pieces corresponding to m sub-pixels fewer than n sub-pixels, and supplies digital data pieces for the n sub-pixels to corresponding memories based on the second video data pieces.
Claims14
A display device comprising:
- a display panel including a plurality of sub-pixels;
- and
- a signal supply circuit supplying parallel data to the display panel,
- wherein the plurality of n sub-pixels have memories, respectively,
- the signal supply circuit, in a first mode, receives first serial data for n sub-pixels, and supplies n-bit parallel data to the respective memories of the n sub-pixels based on the first serial data, and in a second mode, receives second serial data for m sub-pixels fewer than the n sub-pixels, and outputs n-bit parallel data to the respective memories of the n sub-pixels based on the second serial data.
A display device comprising:
- a plurality of pixels comprising n sub-pixels,
- a signal supply circuit supplying one-bit data of n-bit parallel data to corresponding one of the sub-pixels,
- memories provided in the respective sub-pixels and each supplied with corresponding one-bit data, and
- pixel electrodes provided in the respective sub-pixels and each supplied with electric potential caused by one-bit data stored in corresponding one of the memories,
- wherein
- the signal supply circuit, in a first mode, receives n-bit serial data and supplies n-bit parallel data to the respective memories of the n sub-pixels based on the n-bit serial data, and in a second mode, receives m-bit serial data fewer than the n-bit serial data and supplies n-bit parallel data to the respective memories of the n sub-pixels based on the m-bit serial data.
Dependencies are inferred from the claim text.