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US 10,762,420 B2Granted
Self repairing neural network
AssigneeXcelsis Corporation
InventorsSteven L. Teig, Kenneth Duong
Life of this patent
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AssigneeXcelsis Corporation
InventorsSteven L. Teig, Kenneth Duong
Estimating the term…
Some embodiments of the invention provide an integrated circuit (IC) with a defect-tolerant neural network. The neural network has one or more redundant neurons in some embodiments. After the IC is manufactured, a defective neuron in the neural network can be detected through a test procedure and then replaced by a redundant neuron (i.e., the redundant neuron can be assigned the operation of the defective neuron). The routing fabric of the neural network can be reconfigured so that it re-routes signals around the discarded, defective neuron. In some embodiments, the reconfigured routing fabric does not provide any signal to or forward any signal from the discarded, defective neuron, and instead provides signals to and forwards signals from the redundant neuron that takes the defective neuron's position in the neural network. In some embodiments that implement a neural network by re-purposing (i.e., reconfiguring) one or more individual neurons to implement neurons of multiple stages of the neural network, the IC discards a defective neuron by removing it from the pool of neurons that it configures to perform the operation(s) of neurons in one or more stages of neurons, and assigning this defective neuron's configuration(s) (i.e., its machine-trained parameter set(s)) to a redundant neuron. In some of these embodiments, the IC would re-route around the defective neuron and route to the redundant neuron, by (1) supplying machine-trained parameters and input signals (e.g., previous stage neuron outputs) to the redundant neuron instead of supplying these parameters and signals to the defective neuron, and (2) storing the output(s) of the redundant neuron instead of storing the output(s) of the defective neuron.
For a circuit of a device, the circuit comprising a plurality of neurons, a method for configuring (i) neurons on the circuit and (ii) routing fabric between the neurons on the circuit, in order to implement an interconnected arrangement of neurons that defines a neural network that executes on the device, the method comprising:
For an integrated circuit (IC) comprising a plurality of neurons, a method for configuring (i) neurons on the IC and (ii) routing fabric between the neurons on the IC, in order to implement an interconnected arrangement of neurons that defines a neural network, the method comprising:
For a circuit comprising a plurality of neurons, a method for configuring (i) neurons on the circuit and (ii) routing fabric between the neurons on the circuit, in order to implement an interconnected arrangement of neurons that defines a neural network, the method comprising:
A non-transitory machine readable medium storing a program for configuring a plurality of neurons and routing fabric between the neurons to form an interconnected arrangement of neurons that defines a neural network for execution on a device, wherein the plurality of neurons and routing fabric are part of a circuit of the device, the program comprising sets of instructions for:
A non-transitory machine readable medium storing a program for configuring a plurality of neurons and routing fabric between the neurons to form an interconnected arrangement of neurons that defines a neural network, wherein the plurality of neurons and routing fabric are part of an integrated circuit (IC), the program comprising sets of instructions for:
A non-transitory machine readable medium storing a program for configuring a plurality of neurons and routing fabric between the neurons to form an interconnected arrangement of neurons that defines a neural network, wherein the plurality of neurons and routing fabric are part of a circuit, the program comprising sets of instructions for:
Dependencies are inferred from the claim text.