System and method for electrical behavior modeling in a 3D virtual fabrication environment
AssigneeCoventor, Inc.
InventorsMattan Kamon, Kenneth B. Greiner, David M. Fried, Vasanth Allampalli, Yiguang Yan
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Abstract
Modeling of electrical behavior during the virtual fabrication of a semiconductor device structure is discussed. Electrical behavior occurring in a designated region of a semiconductor device structure may be determined during the virtual fabrication process. For example, resistance or capacitance values may be determined within a modeling domain of interest.
Claims20
A non-transitory computer-readable medium holding computing device-executable instructions for determining electrical behavior in a circuit in a semiconductor device structure being virtually fabricated, the circuit including at least one of one or more individual devices and one or more interconnect structures, the instructions when executed causing the computing device to:
- receive a process sequence for a semiconductor device structure to be virtually fabricated, the process sequence including at least one electrical behavior modeling step;
- perform with the computing device a virtual fabrication run for the semiconductor device structure using the process sequence and 2D design data, the virtual fabrication run:
- executing the process sequence, the executing of the process sequence building a 3D structural model of the semiconductor device structure using an implicit geometry representation for the 3D structural model, the implicit geometry representation defining an interface between materials in the 3D structural model without an explicit representation of (x,y,z) coordinate locations of that interface, and
- performing the at least one electrical behavior modeling step to determine electrical behavior data in a designated region of the 3D structural model using the implicit geometry representation without generating a conformal surface or volume mesh from the 3D structural model, and
- display the electrical behavior data determined by the at least one electrical behavior modeling step of the virtual fabrication run in a 3D view of the 3D structural model that indicates a structural origin of the electrical behavior data.
A computing device-implemented method for determining electrical behavior in a circuit in a semiconductor device structure being virtually fabricated, the circuit including at least one of one or more individual devices and one or more interconnect structures, the method comprising:
- receiving a process sequence for a semiconductor device structure to be virtually fabricated, the process sequence including at least one electrical behavior modeling step;
- performing with the computing device a virtual fabrication run for the semiconductor device structure using the process sequence and 2D design data, the virtual fabrication run:
- executing the process sequence, the executing of the process sequence building a 3D structural model of the semiconductor device structure using an implicit geometry representation for the 3D structural model, the implicit geometry representation defining an interface between materials in the 3D structural model without an explicit representation of (x,y,z) coordinate locations of that interface, and
- performing the at least one electrical behavior modeling step to determine electrical behavior data in a designated region of the 3D structural model using the implicit geometry representation without generating a conformal surface or volume mesh from the 3D structural model, and
- displaying the electrical behavior data determined by the at least one electrical behavior modeling step of the virtual fabrication run in a 3D view of the 3D structural model that indicates a structural origin of the electrical behavior data.
A computing device, configured to determine electrical behavior in a circuit in a semiconductor device structure being virtually fabricated, the circuit including at least one of one or more individual devices and one or more interconnect structures, the computing device further comprising:
- a processor;
- a memory holding instructions that when executed perform one or more virtual fabrication runs for the semiconductor device structure using a process sequence and 2D design data, the process sequence including at least one electrical behavior modeling step, the one or more virtual fabrication runs:
- executing the process sequence, the executing of the process sequence building a 3D structural model of the semiconductor device structure using an implicit geometry representation for the 3D structural model, the implicit geometry representation defining an interface between materials in the 3D structural model without an explicit representation of (x,y,z) coordinate locations of that interface, and
- performing the at least one electrical behavior modeling step to determine electrical behavior data in a designated region of the 3D structural model using the implicit geometry representation without generating a conformal surface or volume mesh from the 3D structural model,
- wherein the electrical behavior data determined by the at least one electrical behavior modeling step of the virtual fabrication run is displayed by the computing device in a 3D view of the 3D structural model that indicates a structural origin of the electrical behavior data.
Dependencies are inferred from the claim text.