# US 10,762,034 B2 · Memory-based distributed processor architecture

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- Number: US 10,762,034 B2
- Document ID: US10762034B2
- Status: Granted
- Kind: B2
- Application number: 16/512,590
- Filed: 2019-07-16
- Published: 2019-11-07
- Granted: 2020-09-01
- Earliest claimed: 2017-07-30
- Assignees: NeuroBlade Ltd.
- Applicants: NeuroBlade, Ltd.
- Inventors: Elad Sity; Eliad Hillel
- Web page: https://patentgrep.com/patent/US10762034B2

## CPC

- G06F 11/1658: {Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit}
- G06F 12/06: Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence)
- G06F 8/41: Compilation
- G06F 9/3001: {Arithmetic instructions}
- G06F 9/3885: {using a plurality of independent parallel functional units}
- G06F 9/3889: {controlled by multiple instructions, e.g. MIMD, decoupled access or execute}
- G06F 9/3895: {for complex operations, e.g. multidimensional or interleaved address generators, macros}
- G06F 11/1016: {Error in accessing a memory location, i.e. addressing error}
- G06F 11/102: {Error in check bits}
- G06F 11/16: Error detection or correction of the data by redundancy in hardware
- G06F 11/1616: {where the redundant component is an I/O device or an adapter therefor}
- G06F 13/1657: {Access to multiple memories}
- G06F 15/8038: {Associative processors}
- G06N 3/0464: Convolutional networks [CNN, ConvNet]
- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G11C 11/1655: {Bit-line or column circuits}
- G11C 11/1657: {Word-line or row circuits}
- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/408: Address circuits
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G06F 8/427: {Parsing}
- G06F 8/45: {Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions}
- G06F 2015/765: {Cache}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

## Claims

### Claim 1

A memory chip, comprising:
a plurality of memory banks, each memory bank having a bank row decoder, a bank column decoder, and a plurality of memory sub-banks, each memory sub-bank having a sub-bank row decoder and a sub-bank column decoder for allowing reads and writes to locations on the memory sub-bank, each memory sub-bank comprising:
a plurality of memory mats, each memory mat having a plurality of memory cells, wherein the sub-bank row decoders and the sub-bank column decoders are configured to receive read and write requests from at least one of the bank row decoder and the bank column decoder.

### Claim 2 (depends on 1)

The memory chip of claim 1, wherein each memory sub-bank further has a sub-bank controller configured to determine whether to processor read requests and write requests from a controller of the memory bank.

### Claim 3 (depends on 2)

The memory chip of claim 2, wherein the controller of the memory is synchronized to a system clock.

### Claim 4 (depends on 2)

The memory chip of claim 2, wherein the controllers of the memory sub-banks are not synchronized to a system clock.

### Claim 5 (depends on 1)

The memory chip of claim 1, wherein each sub-bank further has a processor subunit using the sub-bank as a dedicated memory.

### Claim 6 (depends on 5)

The memory chip of claim 5, wherein each processor subunit is configured to access a sub-bank dedicated to the processor subunit using the row decoder and the column decoder of the sub-bank without using the bank row decoder and the bank column decoder.

### Claim 7 (depends on 5)

The memory chip of claim 5, wherein the processor subunit comprises a configurable processor subunit or an accelerator.

### Claim 8

A memory chip, comprising:
a plurality of memory banks, each memory bank having a bank controller and a plurality of memory sub-banks, each memory sub-bank having a sub-bank row decoder and a sub-bank column decoder for allowing reads and writes to locations on the memory sub-bank, each memory sub-bank comprising:
a plurality of memory mats, each memory mat having a plurality of memory cells, wherein the sub-bank row decoders and the sub-bank column decoders are configured to receive read and write requests from the bank controller and process read and write requests received from the bank controller.

### Claim 9 (depends on 8)

The memory chip of claim 8, wherein each memory sub-bank further has a sub-bank controller configured to determine whether to processor read requests and write requests from the bank controller.

### Claim 10 (depends on 9)

The memory chip of claim 9, wherein the bank controller is synchronized to a system clock.

### Claim 11 (depends on 9)

The memory chip of claim 9, wherein the controllers of the memory sub-banks are not synchronized to a system clock.

### Claim 12 (depends on 8)

The memory chip of claim 8, wherein each sub-bank further has a processor subunit using the sub-bank as a dedicated memory.

### Claim 13 (depends on 12)

The memory chip of claim 12, wherein each processor subunit is configured to access a sub-bank dedicated to the processor subunit using the row decoder and the column decoder of the sub-bank without using the bank controller.

### Claim 14

A memory chip, comprising:
a plurality of memory banks, each memory bank having a bank controller for processing reads and writes to locations on the memory bank, each memory bank comprising:
a plurality of memory mats, each memory mat having a plurality of memory cells and having a mat row decoder and a mat column decoder, wherein the mat row decoders and the mat column decoders are configured to process read and write requests from a sub-bank controller, wherein the read and write requests are generated by the sub-bank controller independent from the bank controller.

### Claim 15 (depends on 14)

The memory chip of claim 14, wherein each memory mat further has a comparator configured to determine whether to processor read requests and write requests from the sub-bank controller based on the command address from the bank controller.

### Claim 16 (depends on 14)

The memory chip of claim 14, wherein each memory mat has an assigned address range that is determined by one or more fuses.

### Claim 17 (depends on 16)

The memory chip of claim 16, wherein the one or more fuses are configured to disable a memory mat that is faulty.

### Claim 18 (depends on 14)

The memory chip of claim 14, wherein each sub-bank further has a processor subunit using the sub-bank as a dedicated memory.

### Claim 19

A memory chip, comprising:
a plurality of memory banks, each memory bank having a bank controller, a row decoder, and a column decoder for allowing reads and writes to locations on the memory bank; and
a plurality of buses connecting each controller of the plurality of bank controllers to at least one other controller of the plurality of bank controllers; and
wherein each controller is configured to process data incoming from other controllers before passing the data to the memory bank having the controller.

### Claim 20 (depends on 19)

The memory chip of claim 19, wherein the plurality of buses are configured to be accessed without interruption of data transfers on main buses of the memory banks.

### Claim 21

A memory chip, comprising:
a plurality of memory banks, each memory bank having a bank controller, a row decoder, and a column decoder for allowing reads and writes to locations on the memory bank; and
a plurality of buses connecting each controller of the plurality of bank controllers to at least one other controller of the plurality of bank controllers, wherein each controller is connected to a plurality of other controllers and is configurable for selection of one other of the other controllers for sending or receiving of data.

### Claim 22 (depends on 19)

The memory chip of claim 19, wherein each memory bank comprises a dynamic random access memory bank.

### Claim 23 (depends on 19)

The memory chip of claim 19, wherein each controller is configurable and is configured to determine addresses for reading and writing in the memory bank having the controller.

### Claim 24 (depends on 21)

The memory chip of claim 21, wherein each controller is configured to process data incoming from other controllers before passing the data to the memory bank having the controller.

### Claim 25 (depends on 19)

The memory chip of claim 19, wherein each controller is connected to another spatially adjacent controller.

### Claim 26 (depends on 14)

The memory chip of claim 14, wherein the sub-bank controller is configured to return an error message upon receiving a control signal from the bank controller while the read and write requests are being processed.