Information processing system, and control method of information processing system

An information processing system that is connected to one or a plurality of hosts and a second information processing system, which manages a second ALU (Administrative Logical Unit) connected to the one or plurality of hosts via a second logical path, and a plurality of second SLUs (Subsidiary Logical Units) for receiving I/O (Input/Output) requests from the one or plurality of hosts via the second logical path, and that includes a processor, wherein,

• the processor manages a first ALU connected to the one or plurality of hosts via a first logical path and a plurality of first SLUs that receive I/O requests from the one or plurality of hosts via the first logical path, and builds up a first group including the plurality of first SLUs,
• at least one first SLU of the plurality of first SLUs and at least one second SLU of the plurality of second SLUs compose an HA (High Availability) pair, and the HA pair is provided to the one or plurality of hosts as one volume, and
• the processor evaluates the state of the first logical path on the basis of the pair state of the first SLU that composes the HA pair included in the first group so that priorities with which the one or plurality of hosts issue I/Os to the first logical path can be determined,
• when the number of retries of I/O issuance to the first logical path exceeds a threshold, the processor issues a test I/O to the plurality of first SLUs, and
• when
• the processor receives at least one normal response from one or more first SLUs of the plurality of first SLUs, the processor evaluates the state of the first logical path as “ACTIVE/NON-OPTRIMIZED”, and
• the processor does not receive a normal response from any first SLU of the plurality of first SLUs, the processor evaluates the state of the first logical path as “BLOCK”.

A control method of an information processing system that is connected to one or a plurality of hosts and a second information processing system, which manages a second ALU (Administrative Logical Unit) connected to the one or plurality of hosts via a second logical path, and a plurality of second SLUs (Subsidiary Logical Units) for receiving I/O (Input/Output) requests from the one or plurality of hosts via the second logical path, and that includes a processor, wherein

• the processor manages a first ALU connected to the one or plurality of hosts via a first logical path and a plurality of first SLUs that receive I/O requests from the one or plurality of hosts via the first logical path and a third SLU, and
• builds up a first group including the plurality of first SLUs,
• an HA (High Availability) pair is composed of at least one first SLU of the plurality of first SLUs and at least one second SLU of the plurality of second SLUs, and the HA pair is provided to the one or plurality of hosts as one volume, and
• the processor builds up a second group including the plurality of third SLUs,
• at least one third SLU of the plurality of third SLUs and at least one second SLU of the plurality of second SLUs compose an HA pair, and the HA pair is provided to the one or plurality of hosts as one volume, and
• the processor
• evaluates the state of the first logical path on the basis of the pair state of the first SLU that composes the HA pair included in the first group so that priorities with which the one or plurality of hosts issue I/Os to the first logical path can be determined, and
• determines first priority that the one or plurality of hosts issue I/O to the first SLU via the first logical path, evaluates the state of the first logical path based on the pair state of the plurality of third SLUs that compose the HA pair included in the second group, and determines second priority that the one or plurality of hosts issue I/O to the third SLU via the first logical path.