US 10,762,016 B2Granted

Embedded universal serial bus 2 repeater

AssigneeTexas Instruments Incorporated

InventorsWin Naing Maung, Douglas Edward Wente, Mustafa Ulvi Erdogan, Huanzhang Huang, Saurabh Goyal, Bhupendra Sharma

Life of this patent

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Abstract

Aspects of the disclosure provide for a circuit including a squelch detector having a first input coupled to a first node and configured to receive a positive component of a differential signal with a floating center tap, a second input coupled to a second node and configured to receive a negative component of the differential signal, and an output coupled to a logic circuit, a first resistor coupled between the first node and a third node, a second resistor coupled between the third node and the second node, a third resistor coupled between the first node and a fourth node, a fourth resistor coupled between the fourth node and the second node, a capacitor coupled between the fourth node and a ground terminal, a comparator having a first input coupled to the third node, a second input coupled to a fifth node, and an output coupled to the logic circuit.

Claims16

Dependent claims

A circuit, comprising:

a first amplifier having a first input coupled to a first node, a second input coupled to a second node, a first output, and a second output;
a second amplifier having a first input coupled to the first output of the first amplifier, a second input coupled to the second output of the first amplifier, a first output, and a second output;
a third amplifier having a first input coupled to the first output of the second amplifier, a second input coupled to the second output of the second amplifier, a control input, a first output coupled to a third node, and a second output coupled to a fourth node;
a squelch detector having a first input coupled to the first node, a second input coupled to the second node, and an output;
a first resistor coupled between the first node and a fifth node;
a second resistor coupled between the fifth node and the second node;
a comparator having a first input coupled to the fifth node, a second input coupled to a sixth node, and an output;
and
a logic circuit having a first input coupled to the output of the squelch detector, a second input coupled to the output of the comparator, and an output coupled to the control input of the third amplifier.

6 more elements

A circuit, comprising:

a squelch detector having a first input coupled to a first node, a second input coupled to a second node, and an output, wherein the first node is configured to receive a positive component of a differential input signal with a floating center tap, and wherein the second node is configured to receive a negative component of the differential input signal with the floating center tap;
a first resistor coupled between the first node and a third node;
a second resistor coupled between the third node and the second node;
a third resistor coupled between the first node and a fourth node;
a fourth resistor coupled between the fourth node and the second node;
a first capacitor coupled between the fourth node and a ground terminal;
a comparator having a first input coupled to the third node, a second input coupled to a fifth node, and an output;
and
a logic circuit having a first input coupled to the output of the squelch detector, a second input coupled to the output of the logic circuit, and an output.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/404,494Filed 6 May 2019 · us provisional application
Priority: 30 Aug 2018
Published: US 2020/0073839 A15 Mar 2020
Granted: 1 Sep 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 13/382
Information transfer, e.g. on bus: using universal interface adapter
G06F 13/4004
Bus structure: coupling between buses
G06F 13/4282
Bus transfer protocol, e.g. handshake; Synchronisation: on a serial bus, e.g. I2C bus, SPI bus
G06F 13/4295
On a serial bus, e.g. I2C bus, SPI bus: using an embedded synchronisation