Integrated circuit and data processing system having a configurable cache directory for an accelerator

A method of data processing in a coherent data processing system including a system memory, the method comprising:

• host attach logic communicating memory access requests with the coherent data processing system via a first communication interface and communicating, via a second communication interface, memory access requests and request responses with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from the system memory;
• the host attach logic recording, in a real address-based directory inclusive of contents of the accelerator cache, addresses of data from the system memory accessed by the accelerator unit, wherein the recording includes assigning entries in the real address-based directory based on real addresses utilized to identify storage locations in the system memory;
• and
• configuring at least a number of congruence classes utilized in the real address-based directory based on configuration parameters provided by or on behalf of the accelerator unit.

A design structure tangibly embodied in a storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• host attach logic, including:
• a first communication interface for communicatively coupling the integrated circuit with the coherent data processing system;
• a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from the system memory of the coherent data processing system;
• a set-associative real address-based directory inclusive of contents of the accelerator cache, wherein the real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory;
• and
• directory control logic that configures at least a number of congruence classes utilized in the real address-based directory based on configuration parameters provided by or on behalf of the accelerator unit.