Shared loads at compute units of a processor
AssigneeAdvanced Micro Devices, Inc.
InventorMaxim V. Kazakov
Life of this patent
Estimating the term…
Abstract
A processor reduces bus bandwidth consumption by employing a shared load scheme, whereby each shared load retrieves data for multiple compute units (CUs) of a processor. Each CU in a specified group monitors a bus for load accesses directed to a cache shared by the multiple CUs. In response to identifying a load access on the bus, a CU determines if the load access is a shared load access for its share group. In response to identifying a shared load access for its share group, the CU allocates an entry of a private cache associated with the CU for data responsive to the shared load access. The CU then monitors the bus for the data targeted by the shared load. In response to identifying the targeted data on the bus, the CU stores the data at the allocated entry of the private cache.
Claims20
A method comprising:
- at a first compute unit of a processor, monitoring a bus for a shared load request to a memory device issued by a different compute unit of the processor, wherein the memory device is separate from the first compute unit;
- and
- in response to detecting, at the first compute unit, a first shared load request issued to the memory device by a second compute unit of the processor, allocating a first entry of a first dedicated cache of the first compute unit to store data from the memory device responsive to the first shared load request.
A method, comprising:
- at a first compute unit of a processor, monitoring a bus for data responsive to a shared load request issued by a second compute unit of the processor to a memory device, wherein the memory device is separate from the first compute unit;
- and
- in response to detecting, at the first compute unit, the data from the memory device responsive to the shared load request, storing the data at a first dedicated cache of the first compute unit and a second dedicated cache of the second compute unit.
A processor comprising:
- a bus;
- a plurality of compute units coupled to the bus, the plurality of compute units including a first compute unit and a second compute unit;
- a shared cache coupled to the bus;
- and
- wherein the first compute unit is configured to:
- monitor the bus for a shared load request issued to a memory device by another compute unit of the plurality of compute units, wherein the memory device is separate from the first compute unit;
- and
- in response to detecting a first shared load request issued by the second compute unit to the memory device, allocate a first entry of a first dedicated cache of the first compute unit to store data from the memory device responsive to the first shared load request.
Dependencies are inferred from the claim text.