Apparatus and method for processing an ownership upgrade request for cached data that is issued in relation to a conditional store operation

An apparatus comprising:

• a coherent interconnect used to couple a plurality of processing units with a memory, multiple processing units of the plurality having associated cache storage;
• a snoop unit used to implement a cache coherency protocol when a request received by the coherent interconnect identifies a cacheable memory address within the memory;
• and
• the coherent interconnect being arranged to receive, from a first processing unit having an associated cache storage, an ownership upgrade request specifying a target memory address, the ownership upgrade request indicating that a copy of data at the target memory address, as held in a shared state in the first processing unit's associated cache storage at a time the ownership upgrade request was issued, is required to have its state changed from the shared state to a unique state prior to the first processing circuitry performing a write operation to the data;
• the coherent interconnect being arranged to process the ownership upgrade request by referencing the snoop unit in order to determine whether the first processing unit's associated cache storage is identified as still holding a copy of the data at the target memory address at a time the ownership upgrade request is processed, and in that event to identify a pass condition for the ownership upgrade request independent of information held by contention management circuitry for the target memory address, the contention management circuitry being used to control contended access to a memory address by two or more processing units within the plurality of processing units;
• wherein when, during processing of the ownership upgrade request by the coherent interconnect, the snoop unit determines that the first processing unit's associated cache storage no longer holds a copy of the data at the target memory address, the coherent interconnect is arranged to identify a fail condition for the ownership upgrade request independent of information held by the contention management circuitry for the target memory address.

A method of operating an apparatus that has a plurality of processing units, where multiple processing units of the plurality have associated cache storage, and a coherent interconnect used to couple the plurality of processing units with a memory, comprising:

• employing a snoop unit within the coherent interconnect to implement a cache coherency protocol when a request received by the coherent interconnect identifies a cacheable memory address within the memory;
• employing contention management circuitry to control contended access to a memory address by two or more processing units within the plurality of processing units;
• receiving at the coherent interconnect, from a first processing unit having an associated cache storage, an ownership upgrade request specifying a target memory address, the ownership upgrade request indicating that a copy of data at the target memory address, as held in a shared state in the first processing unit's associated cache storage at a time the ownership upgrade request was issued, is required to have its state changed from the shared state to a unique state prior to the first processing circuitry performing a write operation to the data;
• and
• processing the ownership upgrade request by referencing the snoop unit in order to determine whether the first processing unit's associated cache storage is identified as still holding a copy of the data at the target memory address at a time the ownership upgrade request is processed, and in that event identifying a pass condition for the ownership upgrade request independent of information held by the contention management circuitry for the target memory address;
• wherein when, during processing of the ownership upgrade request, the snoop unit determines that the first processing unit's associated cache storage no longer holds a copy of the data at the target memory address, identifying a fail condition for the ownership upgrade request independent of information held by the contention management circuitry for the target memory address.