Hybrid precise and imprecise cache snoop filtering
AssigneeXilinx, Inc.
InventorsMillind Mittal, Jaideep Dastidar
Life of this patent
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Abstract
Circuits and methods for combined precise and imprecise snoop filtering. A memory and a plurality of processors are coupled to the interconnect circuitry. A plurality of cache circuits are coupled to the plurality of processor circuits, respectively. A first snoop filter is coupled to the interconnect and is configured to filter snoop requests by individual cache lines of a first subset of addresses of the memory. A second snoop filter is coupled to the interconnect and is configured to filter snoop requests by groups of cache lines of a second subset of addresses of the memory. Each group encompasses a plurality of cache lines.
Claims17
A circuit arrangement comprising:
- interconnect circuitry;
- a memory coupled to the interconnect circuitry;
- a plurality of processor circuits coupled to the interconnect circuitry;
- a plurality of cache circuits coupled to the plurality of processor circuits, respectively;
- a first snoop filter coupled to the interconnect and configured to filter snoop requests by individual cache lines of a first subset of addresses of the memory;
- a second snoop filter coupled to the interconnect and configured to filter snoop requests by groups of cache lines of a second subset of addresses of the memory, wherein each group encompasses a plurality of cache lines;
- and
- a control circuit coupled to the first snoop filter and to the second snoop filter, wherein the control circuit is configured to:
- reassign a group of cache lines filtered by the second snoop filter to cache lines filtered by the first snoop filter, wherein reassignment includes evicting the group of cache lines from the second snoop filter and adding the plurality of cache lines of the group to the first snoop filter,
- determine an owner count of a first group of cache lines filtered by the second snoop filter;
- and
- reassign cache lines of the first group of cache lines from the second snoop filter to the first snoop filter in response to the owner count of the first group being equal to 1 and an access count of the first group being greater than zero.
A method comprising:
- caching cache lines of a memory in cache circuits of a plurality of processors;
- filtering by a first snoop filter, snoop requests by individual cache lines of a first subset of addresses of the memory;
- filtering by a second snoop filter, snoop requests by groups of cache lines of a second subset of addresses of the memory, wherein each group encompasses a plurality of cache lines;
- reassigning by a control circuit, a group of cache lines filtered by the second snoop filter to cache lines filtered by the first snoop filter, wherein the reassigning includes evicting the group of cache lines from the second snoop filter and adding the plurality of cache lines of the group to the first snoop filter;
- determining by the control circuit, an owner count of a first group of cache lines filtered by the second snoop filter;
- and
- reassigning cache lines of the first group of cache lines from the second snoop filter to the first snoop filter by the control circuit in response to the owner count of the first group being equal to 1 and an access count of the first group being greater than zero.
Dependencies are inferred from the claim text.