Method and apparatus for memory wear leveling
AssigneeArm Limited
InventorsMudit Bhargava, Joel Thornton Irby, Vikas Chandra
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Abstract
A method and apparatus is provided for wear leveling of a storage medium in an electronic device. Wear leveling is achieved by mapping each logical memory address to a corresponding physical memory address. The mapping information is consistent over an on-period of a power cycle, but changes from one power cycle to another. The mapping information, such as a key value for example, may be stored in non-volatile memory such as, for example, a correlated electron random switch (CES) storage element. The mapping may be obtained by manipulating bits of the logical address to obtain the physical address.
Claims24
An apparatus for wear-leveling of a storage medium of an electrically powered device, wherein the apparatus is supplied with electrical power during on-periods of a plurality of power cycles and comprises:
- a storage element that stores a key value during an off-period or a sleep-period of a power cycle of the plurality of power cycles;
- address translation logic circuitry configured to map a logical address to a physical address in the storage medium of the electrically powered device, wherein the mapping is obtained by manipulating bits of the logical address dependent upon the key value, and wherein the key value is the same for a plurality of logical addresses in an address space;
- and
- key update logic circuitry configured to update the key value stored in the storage element;
- wherein the key value is updated, by the key update logic circuitry, during a power-up, sleep or power-off operation of one or more power cycles of the plurality of power cycles,
- the mapping of the logical address is varied from one power cycle to another of the one or more power cycles, the logical address being mapped to a first physical address prior to a first power cycle of the one or more power cycles, and
- the logical address being mapped to a second physical address, different from the first physical address, after the first power cycle, to distribute memory accesses across the storage medium of the electrically powered device and reduce failure of memory cells of the storage medium of the electrically powered device, and
- wherein the storage element, address translation logic circuitry and key update logic circuitry are implemented in hardware.
A method of controlling usage of a storage medium of an electrically powered device, the method comprising:
- receiving, by address translation logic circuitry of the electrically powered device, a logical memory address;
- mapping, by the address translation logic circuitry, the logical memory address to a physical memory address in the storage medium, wherein the mapping is obtained by manipulating the logical memory address dependent upon a key value;
- accessing, by the electrically powered device, the storage medium at the physical memory address;
- and
- updating, by key update logic circuitry of the electrically powered device, the key value during a power-up, sleep or power-off operation of one or more power cycles of the electrically powered device,
- wherein the mapping of the logical memory address is varied from one power cycle to another of the one or more power cycles,
- the logical memory address being mapped to a first physical memory address prior to a first power cycle of the one or more power cycles, and
- the logical memory address being mapped to a second physical memory address, different from the first physical memory address, after the first power cycle, to distribute memory accesses across the storage medium and reduce failure of memory cells of the storage medium.
Dependencies are inferred from the claim text.