Nonvolatile memory device and operation method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsBong-Kil Jung, Hyunggon Kim, Donghoon Jeong, Myung-Hoon Choi
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Abstract
An operation method of a nonvolatile memory device includes receiving control signals and a data signal from external of the nonvolatile memory device, generating debugging information based on the control signals and the data signal, receiving a debugging information request from external of the nonvolatile memory device, and outputting the debugging information in response to the debugging information request.
Claims20
An operation method of a nonvolatile memory device including a signal storage circuit, a debugging information generator, and a debugging information register, the method comprising:
- receiving, by the signal storage circuit, control signals and a data signal from external of the nonvolatile memory device;
- generating, by the debugging information generator, debugging information based on the control signals and the data signal;
- receiving a debugging information request from external of the nonvolatile memory device;
- and
- outputting, by the debugging information register, the debugging information in response to the debugging information request.
A nonvolatile memory device comprising:
- a signal storage circuit configured to store control signals and a data signal received from external of the nonvolatile memory device;
- a debugging information generator configured to generate debugging information based on the stored control signals and the stored data signal;
- and
- a debugging information register configured to output the debugging information in response to a debugging information request from external of the nonvolatile memory device.
A nonvolatile memory package comprising:
- an interface chip configured to receive control signals and a data signal through an external channel connected with a memory controller;
- a first nonvolatile memory device configured to receive first control signals and a first data signal through a first internal channel connected with the interface chip;
- and
- a second nonvolatile memory device configured to receive second control signals and a second data signal through a second internal channel connected with the interface chip,
- wherein the interface chip comprises a debugging support circuit configured to output first and second debugging information in response to a debugging information request from the memory controller, and
- wherein the debugging support circuit is configured to generate the first debugging information associated with the first nonvolatile memory device from the first control signals and the first data signal, and to generate the second debugging information associated with the second nonvolatile memory device from the second control signals and the second data signal.
Dependencies are inferred from the claim text.