Collision detection for slave storage devices
AssigneeWestern Digital Technologies, Inc.
InventorsMark Robert Hicks, George Christopher Sneed
Life of this patent
Estimating the term…
Abstract
A method includes transmitting, by a controller of a storage device, a first bit on a data line. The method further includes responsive to transmitting the first bit on the data line, determining, by the controller, a line level of the data line. The method further includes responsive to determining the line level of the data line, determining, by the controller, whether the line level of the data line corresponds to the first bit and responsive to determining that the line level of the data line does not correspond to the first bit, determining, by the controller, that a collision has occurred on the data line.
Claims24
A method, comprising:
- receiving, by a controller of a storage device, an indication of a transmit buffer empty event, wherein the storage device comprises master and slave storage devices;
- transmitting, by the controller, data into a transmit holding register;
- determining, by the controller, when an acknowledgement is received on a data line, wherein the acknowledgement indicates a successful transmission of data to the transmit holding register;
- transmitting, by the controller, a first bit on the data line in response to receiving the acknowledgement;
- determining, by the controller, a line level of the data line;
- determining, by the controller, that a data collision has not occurred when the first bit corresponds to the line level;
- and
- transmitting, by the controller, a second bit on the data line based on determining that a data collision has not occurred.
A device comprising:
- a storage element;
- an interface coupled to a bus;
- one or more storage devices coupled to the bus;
- an arbitration module configured to detect data collisions between the one or more storage devices;
- and
- a controller configured to:
- transmit a first bit on the data line in response to receiving an acknowledgement from a transmit holding register indication successful receipt of data;
- determine a line level of the data line;
- determine that a data collision has not occurred when the first bit corresponds to the line level;
- and
- transmit a second bit on the data line based on determining that a data collision has not occurred.
A storage device comprising:
- a controller;
- a data bus;
- an interface coupled to the data bus;
- a plurality of memory devices coupled to and configured to share the data bus;
- and
- means for enabling the plurality of memory devices to detect data collisions on the data bus;
- and
- an arbitration module configured to release data to a transmit holding register when a line level of the data bus corresponds to a first bit of a data bus.
A method comprising:
- transmitting, by a controller of a storage device, a first bit on a data line;
- determining, by the controller, a line level of the data line after transmitting the first bit to the data line;
- determining, by the controller, whether the line level of the data line corresponds to the first bit;
- determining, by the controller, that a collision occurred on the data line in response to determining that the line level of the data line does not correspond to the first bit;
- receiving an indication of a transmit buffer empty event;
- outputting the first bit into a transmit holding register of the controller, wherein transmitting the first bit on the data line is in response to outputting the first bit into the transmit holding register;
- and
- generating, by the controller, an interrupt based on the collision, wherein the interrupt delays future transmission of a second bit.
A storage device comprising:
- a storage element;
- an interface coupled to a data bus;
- a controller configured to:
- transmit a first bit on a data line;
- determine a line level of the data line after transmitting the first bit to the data line;
- determine whether the line level of the data line corresponds to the first bit;
- determine that a collision occurred on the data line in response to determining that the line level of the data line does not correspond to the first bit;
- and
- generate an interrupt based on the collision, wherein the interrupt delays future transmission of a second bit by stopping transmitting on the data line until the data line has undergone a reset, and wherein the reset occurs when a logical “1” is written to the data line during a first clock cycle of a clock signal;
- and
- an arbitration module configured to release data to a transmit holding register when a line level of the data bus corresponds to a first bit of a data bus.
Dependencies are inferred from the claim text.