# US 10,761,918 B2 · Method to handle corrected memory errors on kernel text

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,761,918 B2
- Document ID: US10761918B2
- Status: Granted
- Kind: B2
- Application number: 15/955,747
- Filed: 2018-04-18
- Published: 2019-10-24
- Granted: 2020-09-01
- Earliest claimed: 2018-04-18
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Aravinda Prasad; Mahesh J. Salgaonkar
- Web page: https://patentgrep.com/patent/US10761918B2

## CPC

- G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)}
- G06F 9/45558: {Hypervisor-specific management and integration aspects}
- G06F 9/545: {where tasks reside in different layers, e.g. user- and kernel-space}
- G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 11/3668: Testing of software
- G06F 2009/45583: {Memory management, e.g. access or allocation}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Embodiments of the present invention facilitate handling corrected memory errors on kernel text. An example computer-implemented method includes identifying a correctable error (CE) in a physical error location of a memory and a kernel function impacted by the CE. The identified kernel function includes a plurality of instructions including a first instruction of the identified kernel function at a first physical memory location in a first region of the memory. The first region includes the physical error location. The plurality of instruction is loaded to a second region of the memory. The loading includes storing the first instruction of the identified kernel function at a second physical memory location in the second region of the memory. The first physical memory location in the first region of the memory is updated to include an instruction to branch to the second physical memory location in the second region of the memory.

## Claims

### Claim 1

A computer-implemented method comprising:
identifying a correctable error (CE) in a physical error location of a memory;
identifying a kernel function impacted by the CE, the identified kernel function comprising a plurality of instructions in a first region of the memory, the plurality of instructions including a first instruction of the identified kernel function at a first physical memory location in the first region of the memory, the first region including the physical error location, wherein the first physical memory location is different than the physical error location;
loading the plurality of instructions to a second region of the memory, the loading including storing the first instruction of the identified kernel function at a second physical memory location in the second region of the memory;
updating the first physical memory location in the first region of the memory to include an instruction to branch to the second physical memory location in the second region of the memory;
receiving a request to access the identified kernel function at the first physical memory location subsequent to the loading and the updating; and
accessing the first physical memory location and performing the instruction to branch to the second physical memory location in response to receiving the request to access the identified kernel function at the first physical memory location.

### Claim 2 (depends on 1)

The computer-implemented method of claim 1, wherein the identifying a kernel function, loading and updating are performed by a kernel of a processor.

### Claim 3 (depends on 2)

The computer-implemented method of claim 2, wherein the kernel is a hypervisor.

### Claim 4 (depends on 2)

The computer-implemented method of claim 2, wherein the kernel is implemented by firmware.

### Claim 5 (depends on 1)

The computer-implemented method of claim 1, wherein the identifying a CE comprises receiving a notification from a memory controller.

### Claim 6 (depends on 1)

The computer-implemented method of claim 1, wherein the identifying a CE comprises receiving a notification from a processor.

### Claim 7 (depends on 1)

The computer-implemented method of claim 1, wherein the first region of the memory and the second region of the memory comprise protected memory.

### Claim 8

A system comprising:
a memory having computer readable instructions; and
one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
identifying a correctable error (CE) in a physical error location of a memory;
identifying a kernel function impacted by the CE, the identified kernel function comprising a plurality of instructions in a first region of the memory, the plurality of instructions including a first instruction of the identified kernel function at a first physical memory location in the first region of the memory, the first region including the physical error location, wherein the first physical memory location is different than the physical error location;
loading the plurality of instructions to a second region of the memory, the loading including storing the first instruction of the identified kernel function at a second physical memory location in the second region of the memory;
updating the first physical memory location in the first region of the memory to include an instruction to branch to the second physical memory location in the second region of the memory;
receiving a request to access the identified kernel function at the first physical memory location subsequent to the loading and the updating; and
accessing the first physical memory location and performing the instruction to branch to the second physical memory location in response to receiving the request to access the identified kernel function at the first physical memory location.

### Claim 9 (depends on 8)

The system of claim 8, wherein the identifying a kernel function, loading and updating are performed by a kernel of one of the one or more processors.

### Claim 10 (depends on 9)

The system of claim 9, wherein the kernel is a hypervisor.

### Claim 11 (depends on 9)

The system of claim 9, wherein the kernel is implemented by firmware.

### Claim 12 (depends on 8)

The system of claim 8, wherein the identifying a kernel function, loading, and updating are performed by an operating system of one of the one or more processors.

### Claim 13 (depends on 8)

The system of claim 8, wherein the identifying a CE comprises receiving a notification from a memory controller.

### Claim 14 (depends on 8)

The system of claim 8, wherein the identifying a CE comprises receiving a notification from one of the one or more processors.

### Claim 15 (depends on 8)

The system of claim 8, wherein the first region of the memory and the second region of the memory comprise protected memory.

### Claim 16

A computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising:
identifying a correctable error (CE) in a physical error location of a memory;
identifying a kernel function impacted by the CE, the identified kernel function comprising a plurality of instructions in a first region of the memory, the plurality of instructions including a first instruction of the identified kernel function at a first physical memory location in the first region of the memory, the first region including the physical error location, wherein the first physical memory location is different than the physical error location;
loading the plurality of instructions to a second region of the memory, the loading including storing the first instruction of the identified kernel function at a second physical memory location in the second region of the memory;
updating the first physical memory location in the first region of the memory to include an instruction to branch to the second physical memory location in the second region of the memory;
receiving a request to access the identified kernel function at the first physical memory location subsequent to the loading and the updating; and
accessing the first physical memory location and performing the instruction to branch to the second physical memory location in response to receiving the request to access the identified kernel function at the first physical memory location.

### Claim 17 (depends on 16)

The computer program product of claim 16, wherein the identifying a kernel function, loading and updating are performed by a kernel.

### Claim 18 (depends on 17)

The computer program product of claim 17, wherein the kernel is a hypervisor.

### Claim 19 (depends on 16)

The computer program product of claim 16, wherein the first region of the memory and the second region of the memory comprise protected memory.