Optimizing memory fences based on workload

A computer program product including one or more computer readable storage mediums correctively storing program instructions that are executable by a processor or programmable circuitry to cause the processor or programmable circuitry to perform operations comprising:

• determining whether to execute a target program on a single hardware thread or a plurality of hardware threads;
• and
• assigning one of a light-weight memory fence and a heavy-weight memory fence as a memory fence in the target program based on whether to execute the target program on the single hardware thread or the plurality of hardware threads, wherein at least one of the light-weight memory fence and the heavy-weight memory fence are configured to provide memory access based on visibility;
• wherein the light-weight memory fence is assigned in response to determining to execute the target program on the single hardware thread, and the heavy-weight memory fence is assigned in response to determining to execute the target program on the plurality of hardware threads.

An apparatus comprising:

• a processor or a programmable circuitry, and
• one or more computer readable mediums collectively including instructions that, when executed by the processor or the programmable circuitry, cause the processor or the programmable circuitry to:
• determine whether to execute a target program on a single hardware thread or a plurality of hardware threads;
• and
• assign one of a light-weight memory fence and a heavy-weight memory fence as a memory fence in the target program based on whether to execute the target program on the single hardware thread or the plurality of hardware threads, wherein at least one of the light-weight memory fence and the heavy-weight memory fence are configured to provide memory access based on visibility;
• wherein the light-weight memory fence is assigned in response to determining to execute the target program on the single hardware thread, and the heavy-weight memory fence is assigned in response to determining to execute the target program on the plurality of hardware threads.