Processors, methods, systems, and instruction conversion modules for instructions with compact instruction encodings due to use of context of a prior instruction

A method performed by a processor comprising:

• decoding a first prior instruction having at least a first context, wherein the first prior instruction is an arithmetic instruction;
• decoding a first subsequent instruction, which is after the first prior instruction in original program order, the first subsequent instruction having an opcode and a first field having a first value, wherein the first field is allowed by the opcode to have either the first value or a second value that is different than the first value;
• using the first context of the first prior instruction to determine a second context for the first subsequent instruction based on the first field having the first value;
• decoding a second prior instruction having at least a first context, wherein the second prior instruction is another instance of the arithmetic instruction;
• decoding a second subsequent instruction, which is after the second prior instruction in the original program order, the second subsequent instruction having a first field having the second value, the second subsequent instruction having an opcode that is identical to the opcode of the first subsequent instruction, but the second subsequent instruction having a shorter length in bits than the first subsequent instruction;
• not using the first context of the second prior instruction to determine a second context for the second subsequent instruction based on the first field of the second subsequent instruction having the second value;
• and
• executing the first prior instruction, including performing an arithmetic operation on source data indicated by the first prior instruction to produce a result, and storing the result of the first prior instruction in a destination register.

A computer system comprising:

• an interconnect;
• a dynamic random access memory (DRAM) coupled with the interconnect;
• and
• a processor coupled with the interconnect, the processor including:
• a decode unit to decode:
• a prior instruction that is to have at least a first context, wherein the prior instruction is an arithmetic instruction;
• and
• a subsequent instruction, which is to be after the prior instruction in original program order, the subsequent instruction having an opcode and a field that is allowed by the opcode to have either one of at least a first value and a second value, the decode unit, when the field has the first value, to use the first context of the prior instruction to determine a second context for the subsequent instruction, the decode unit, when the field has the second value, not to use the first context of the prior instruction to determine the second context for the subsequent instruction, wherein a length in bits of an encoding of the subsequent instruction is shorter when the field has the first value than when the field has the second value;
• and
• at least one execution unit coupled with the decode unit, the at least one execution unit to perform the prior instruction and the subsequent instruction, wherein to perform the prior instruction includes to perform an arithmetic operation on source data indicated by the prior instruction and to store a result of the arithmetic operation in a destination register.

An article of manufacture comprising a non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium storing a first prior instruction, a first subsequent instruction, a second prior instruction, and a second subsequent instruction, the first and second prior and the first and second subsequent instructions, if performed by a machine, cause the machine to perform operations comprising to:

• decode the first prior instruction which is to have at least a first context, wherein the first prior instruction is an arithmetic instruction;
• decode the first subsequent instruction, which is to be after the first prior instruction in original program order, the first subsequent instruction having an opcode and a first field that is to have a first value, wherein the first field is allowed by the opcode to have either the first value or a second value that is different than the first value;
• use the first context of the first prior instruction to determine a second context for the first subsequent instruction when the first field has the first value;
• decode the second prior instruction which is to have at least a first context;
• decode the second subsequent instruction, which is to be after the second prior instruction in the original program order, the second subsequent instruction having a first field which is to have the second value, the second subsequent instruction having an opcode that is identical to the opcode of the first subsequent instruction, but the second subsequent instruction having a shorter length in bits than the first subsequent instruction;
• and
• not use the first context of the second prior instruction to determine a second context for the second subsequent instruction when the first field of the second subsequent instruction has the second value;
• and
• execute the first prior instruction, including to perform an arithmetic operation on source data of the first prior instruction to produce a result, and to store the result of the first prior instruction in a destination register of the first prior instruction.