Systems and methods for implementing core level predication within a machine perception and dense algorithm integrated circuit

A method for implementing an integrated circuit with core-level predication, the method comprising:

• implementing a plurality of processing cores of an integrated circuit, wherein each of the plurality of cores includes:
• (i) a predicate stack defined by a plurality of single-bit registers that operate together based on one or more of logical connections and physical connections of the plurality of single-bit registers,
• wherein:
• the predicate stack of each of the plurality of processing cores includes a top of stack single-bit register of the plurality of single-bit registers having a bit entry value that controls whether select instructions to the given processing core of the plurality of processing cores are executed;
• and
• (ii) an enable bit that operates outside of the predicate stack and that controls an ON/OFF state of a given processing core of the plurality of processing cores,
• wherein:
• a conditional loop break if evaluated to TRUE causes an execution of a disable instruction that:
• (a) stops the execution of the instructions of a loop body by the given processing core,
• (b) changes a value of the enable bit, and
• (c) disables the given processing core and changes the given processing core from an ON state to an OFF state,
• the execution of the disable instruction changes a bit entry value of the enable bit of the given processing core from 1 to 0 or 0 to 1 according to a binary system, and
• a subsequent execution of an enable instruction that is paired with the disable instruction causes a re-enablement of the given processing core and changes the bit entry value of the enable bit.