Linear feedback shift register for a reconfigurable logic unit

An apparatus, comprising:

• a plurality of configurable logic blocks including a first digital signal processing (DSP) slice and a second DSP slice;
• and
• an interconnect configured to couple the plurality of configurable logic blocks;
• wherein the first DSP slice is coupled to an input of at least the second DSP slice via an output of the first DSP slice, the first DSP slice comprising:
• a plurality of configurable logic units configured to perform an operation;
• a random value generator configured to generate a random value;
• an adder coupled to at least one of the plurality of configurable logic units and the random value generator and configured to generate a sum based on an output value of the configurable logic unit and the random value;
• a shift register coupled to the adder and configured to trim the sum by shifting a number of bits to generate shifted data, wherein the number of bits shifted is based at least on a mode of the operation;
• and
• an operand register having an operand input coupled to at least one of the plurality of configurable logic units and configured to output the shifted data to the output of the first DSP slice.

A method comprising:

• receiving, by a first configurable logic unit, first and second operands;
• performing, by the first configurable logic unit, an operation to generate an operation value based at least on the first and second operands;
• generating, by a random value generator, a random value;
• adding, by an adder, the random value generator and the operation value to generate a sum;
• and
• trimming the sum, by a shift register, by shifting the sum by a number of bits to generate shifted data at an output of the configurable logic unit, wherein the number of bits shifted is based at least on a mode of the operation.