Information processing device and information processing method

A computer-implemented information processing method comprising:

• storing, within a first arithmetic package including a first arithmetic circuit and a second arithmetic circuit, data input to and output from the second arithmetic circuit in accordance with a procedure of maintaining consistency between the data input to and output from the second arithmetic circuit and data stored in circuits other than the second arithmetic circuit;
• transmitting, to a second arithmetic package, information indicating start of transmission of transmission data from the second arithmetic circuit to a fourth arithmetic circuit of the second arithmetic package;
• writing the transmission data to a first cache memory;
• restricting use of the first cache memory by data other than the transmission data;
• and
• storing, within the second arithmetic package including a third arithmetic circuit and the forth arithmetic circuit, data input to and output from the fourth arithmetic circuit in accordance with a procedure of maintaining consistency between the data input to and output from the fourth arithmetic circuit and data stored in circuits other than the fourth arithmetic circuit;
• and
• reading, with the second arithmetic package, the transmission data via a second cache memory when the second arithmetic package receives the information indicating the start of the transmission.

An information processing device comprising:

• a first package including a first arithmetic circuit, first cache memory and a transmitting circuit;
• and
• second package including a second arithmetic circuit, second cache memory and a receiving circuit, wherein
• the first arithmetic circuit is configured to provide transfer data to the first cache memory that is destined for the second cache memory;
• the transmitting circuit configured to transmit to the receiving circuit an indication of a data transfer of the transfer data and to restrict use of the first cache memory for data other than the transfer data during the data transfer;
• and
• the receiving circuit configured to receive the indication of the data transfer, to acquire the transfer data stored in the first cache memory and to store the acquired transfer data in the second cache memory.