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US 10,761,819 B2Granted
Optimizing structures to fit into a complete cache line
AssigneeIntel Corporation
InventorsZhigang Gong, Wenqing Fu, Peng Li, Can Que, Zhiwen Wu
Life of this patent
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Abstract
An input data structure of a first size may be converted to a plurality of data structures of a second size smaller than the first size. The data structures of the second size are realigned such that each of the plurality of data structures fits in one cache line. The realigned data structures are compiled for use in a vector machine.
Claims20
A method comprising:
- converting an input data structure of a first size to a plurality of data structures of a second size smaller than said first size;
- transferring one or more values between said plurality of data structures of said second size to determine a plurality of reordered data structures, wherein each of said plurality of reordered data structures fits in one cache line;
- and
- compiling with said plurality of reordered data structures for use in a vector machine.
1 more element
One or more non-transitory computer readable media storing instructions to perform a sequence comprising:
- converting an input data structure of a first size to a plurality of data structures of a second size smaller than said first size;
- transferring one or more values between said plurality of data structures of said second size to determine a plurality of reordered data structures, wherein each of said plurality of reordered data structures fits in one cache line;
- and
- compiling with said plurality of reordered data structures for use in a vector machine.
1 more element
An apparatus comprising:
- a processor to convert an input data structure of a first size to a plurality of data structures of a second size smaller than said first size, transfer one or more values between said plurality of data structures of said second size to determine a plurality of reordered data structures, wherein each of said plurality of reordered data structures fits in one cache line, and compile with said plurality of reordered data structures for use in a vector machine;
- and
- a memory coupled to said processor.
Dependencies are inferred from the claim text.