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US 10,761,806 B2Granted
Transcendental calculation unit apparatus and method
OwnerMitchell K. Alsupinventor
Life of this patent
Estimating the term…
Abstract
A Transcendental Calculation Unit includes a Configuration Table storing a set of constants and provide a selected one of the constants, a Power Series Multiplier that iteratively develops a power series, a Coefficient Series Multiplier and Accumulator that develops an accumulated product of the power series and the constant, and a Round and Normalize Stage that rounds the accumulated product and normalizes rounded product.
Claims11
A processor comprising a floating point transcendental calculation unit, said floating point transcendental calculation unit comprising:
- a coefficient table configured:
- to store a plurality of predetermined constants, C, each at a unique opcode x m-bit index;
- and
- in response to receiving a coefficient selection Index, k, to provide Ck;
- a power series multiplier configured:
- to receive a n-bit floating point reduced argument, r;
- and
- iteratively to develop a power series, rk;
- a coefficient series multiplier and accumulator configured:
- to develop a series of products, Ck×rk;
- and
- to accumulate said series of products into a sum;
- a round and normalize stage configured:
- to round said accumulated sum;
- and
- to normalize said rounded accumulated sum;
- a control circuit configured, selectively:
- to apply to said coefficient table an index comprising said opcode, a selected m-bit portion of a floating point number, F, and said coefficient selection index, k;
- to apply to said power series multiplier said reduced argument, r;
- to apply to said coefficient series multiplier and accumulator a sequence of Ck and rk;
- and
- to apply to said round and normalize stage the accumulated sum.
19 more elements
A processor comprising a floating point transcendental calculation unit, said floating point transcendental calculation unit comprising:
- a coefficient table configured:
- to store a plurality of predetermined constants, C, each at a unique opcode x m-bit index, and
- in response to receiving a coefficient selection index, k, to provide Ck;
- a multiplier configured to operate as a selective one of:
- a power series multiplier configured:
- to receive an n-bit floating point reduced argument, r;
- and
- iteratively to develop a power series, rk;
- and
- a coefficient series multiplier and accumulator configured:
- to develop a series of products, Ck×rk;
- and
- to accumulate said series of products into a sum;
- a round and normalize stage configured:
- to round said accumulated sum;
- and
- to normalize said rounded accumulated sum;
- and
- a control circuit configured, selectively:
- to apply to said coefficient table a coefficient selection index comprising said opcode, a selected m-bit portion of a floating point number, F;
- to apply to said power series multiplier a reduced arguments, r;
- to apply to said coefficient series multiplier and accumulator a sequence of Ck and rk;
- and
- to apply to the round and normalize stage the accumulated sum.
21 more elements
A processor comprising a floating point calculation unit, said floating point calculation unit comprising:
- a coefficient table configured:
- to store a plurality of predetermined constants, C, each at a unique m-bit index;
- and
- in response to receiving a coefficient selection index, k, to provide Ck;
- a multiplier configured to operate as a vertically split multiplier:
- to receive a triple precision constant;
- to receive an intermediate result;
- to produce a high precision product of the triple precision constant and the intermediate result;
- and
- to produce a right multiplier product, a left multiplier product, and a middle multiplier product and shift the left multiplier product and the right multiplier product to align with the middle multiplier product and deliver a sum as the precision salvaged reduced argument;
- and
- a control circuit configured, selectively:
- to apply to said coefficient table a coefficient selection index, k, comprising a selected m-bit portion of a floating point number, F;
- and
- to apply a precision salvaging argument reduction sequence to said operand.
12 more elements
In a processor, a floating point calculation unit comprising:
- a coefficient table configured:
- to store a plurality of predetermined constants, C, each at a unique m-bit index;
- and
- in response to receiving a coefficient selection index, k, to provide Ck;
- a multiplier configured:
- to receive a double width constant;
- to receive an intermediate result;
- and
- to produce a higher precision multiplier product and a lower precision multiplier product and to shift the lower precision multiplier product to align with the higher precision multiplier product and deliver a sum as the higher precision multiplier product;
- and
- a control circuit configured, selectively:
- to apply to said coefficient table a coefficient selection index, k, comprising a selected m-bit portion of a floating point number, F;
- and
- to apply a high precision multiplication sequence to said operand.
11 more elements
Dependencies are inferred from the claim text.