Reduced floating-point precision arithmetic circuitry

A method to perform floating-point multiplication comprising:

• receiving a plurality of input signals at floating-point multiplication circuitry;
• generating, using the floating-point multiplication circuitry, a first partial product of a first subset of the plurality of input signals;
• generating, using the floating-point multiplication circuitry, a second partial product of a second subset of the plurality of input signals;
• selectively inserting zeros into the first and second partial products, using a plurality of multiplexers, to generate carry and sum signals;
• receiving the generated sum and carry signals at a plurality of prefix networks to output generate signals;
• generating, using sum generation circuitry, sum-plus-zero, sum-plus-one, and sum-plus-two signals based at least in part on the output generate signals and the sum and carry signals;
• and
• receiving a selection signal that indicates a type of operation to be performed by the floating-point multiplication circuitry by selecting between:
• a single-precision floating-point operation on the plurality of input signals with the plurality of input signals representing a plurality of single-precision floating-point numbers using the first and second partial products, wherein the single-precision floating-point operation is based at least in part on the output generate signals and the carry and sum signals,
• a half-precision floating-point operation on the plurality of input signals with the plurality of input signals representing a plurality of half-precision floating-point numbers using the first and second partial products, wherein the half-precision floating-point operation is based at least in part on the output generate signals and the carry and sum signals, and
• a fixed-point operation on the plurality of input signals with the plurality of input signals representing a plurality of fixed-point numbers.

Variable-precision multiplication circuitry comprising:

• a plurality of input ports that receives a plurality of numbers as single-precision floating-point numbers, half-precision floating-point numbers, or fixed-point numbers;
• a selection signal input that receives a selection signal that indicates whether the plurality of numbers are single-precision floating-point numbers, half-precision floating-point numbers, or fixed-point numbers;
• a plurality of arithmetic operators that receives the plurality of numbers and selectively operates in a plurality of modes based at least in part on the selection signal, wherein a first mode of the plurality of modes comprises a single-precision mode that receives the plurality of numbers as single-precision floating-point numbers, a second mode of the plurality of modes comprises a reduced-precision mode that receives the plurality of numbers as reduced-precision floating-point numbers, and a third mode of the plurality of modes comprises a fixed-point mode that receives the plurality of numbers as fixed-point numbers, wherein the plurality of arithmetic operators generates a plurality of partial products based at least in part on plurality of numbers;
• a plurality of multiplexers selectively insert zeros into the plurality of partial products to generate sum and carry signals;
• a plurality of prefix networks, wherein each prefix network receives respective sum and carry signals and generates and outputs generate signals;
• sum generation circuitry that generates sum-plus-zero, sum-plus-one, and sum-plus-two signals based at least in part on the output generate signals and the carry and sum signals;
• and
• a plurality of output ports that outputs a plurality of outputs, wherein the plurality of outputs is based at least in part on a first quantity of represented numbers in the single-precision mode or a second quantity of represented numbers in the reduced-precision mode, wherein the plurality of outputs are based at least in part on the output generate signals and the carry and sum signals.