Forced idling of memory subsystems

A computing device, comprising:

• a memory subsystem including a memory;
• and
• a processor coupled to the memory subsystem, and configured with processor-executable instructions to:
• set the memory subsystem to an active power mode;
• determine a period of time to force the memory subsystem into a low power mode by using open loop control based on a determined actual frequency of the memory subsystem and a frequency determined by a dynamic clock and voltage scaling (DCVS) unit;
• determine an amount of power saved by the memory subsystem in the low power mode for the determined period of time;
• determine an amount of power the memory subsystem consumes entering and exiting the low power mode;
• force the memory subsystem into the low power mode for the determined period of time in response to determining that the amount of power saved by the memory subsystem in the low power mode for the determined period is greater than the amount of power consumed by the memory subsystem entering and exiting the low power mode;
• and
• inhibit memory access requests such that the memory subsystem is prevented from executing any memory access requests during the low power mode.

A non-transitory computer readable storage medium having stored thereon processor-executable software instructions configured to cause a processor of a computing device to perform operations comprising:

• setting a memory subsystem to an active power mode;
• determining a period of time to force the memory subsystem into a low power mode by using open loop control based on a determined actual frequency of the memory subsystem and a frequency determined by a dynamic clock and voltage scaling (DCVS) unit;
• determining an amount of power saved by the memory subsystem in the low power mode for the determined period of time;
• determining an amount of power the memory subsystem consumes entering and exiting the low power mode;
• forcing the memory subsystem into the low power mode for the determined period of time in response to determining that the amount of power saved by the memory subsystem in the low power mode for the determined period of time is greater than the amount of power consumed by the memory subsystem entering and exiting the low power mode;
• and
• inhibiting memory access requests such that the memory subsystem is prevented from executing any memory access requests during the low power mode.

A computing device, comprising:

• means for setting a memory subsystem to operate in an active power mode;
• means for determining a period of time to force the memory subsystem into a low power mode by using open loop control, wherein the means for determining the period of time to force the memory subsystem into a low power mode by using open loop control comprises means for determining an actual frequency of the memory subsystem and a dynamic clock and voltage scaling (DCVS) unit;
• means for determining an amount of power saved by the memory subsystem in the low power mode for the determined period of time;
• means for determining an amount of power the memory subsystem consumes entering and exiting the low power mode;
• means for forcing the memory subsystem into the low power mode for the determined period of time in response to determining that the amount of power saved by the memory subsystem in the low power mode for the determined period is greater than the amount of power consumed by the memory subsystem entering and exiting the low power mode;
• and
• means for inhibiting memory access requests such that the memory subsystem is prevented from executing any memory access requests during the low power mode.