Memory system including a plurality of chips and a selectively-connecting bus

A memory system comprising:

• a nonvolatile semiconductor memory including a first chip and a second chip;
• a controller configured to be connectable to a host, the controller including a first command queue and a second command queue, the second command queue having higher priority than the first command queue;
• and
• a bus configured to be switched to a first connection state or to a second connection state, the first connection state being a state in which the controller is electrically connected to the first chip, the second connection state being a state in which the controller is electrically connected to the second chip,
• wherein the controller is configured to:
• receive, in sequence, a first command and a second command from the host;
• perform, in sequence, a first process corresponding to the first command and a second process corresponding to the second command, the first process being a process in which the controller converts a logical address included in the first command to a physical address and specifies a first destination chip of the first command in accordance with the converted physical address, the second process being a process in which the controller converts a logical address included in the second command to a physical address and specifies a second destination chip of the second command in accordance with the converted physical address;
• divide the first command into a set of first sub-commands, each of the first sub-commands in the set of first sub-commands being associated with the first destination chip which is specified for the first command in the first process;
• divide the second command into a set of second sub-commands each of the second sub-commands in the set of second sub-commands being associated with the second destination chip which is specified for the second command in the second process;
• execute one of the first sub-commands divided from the first command in the first process;
• compare the second destination chip of the second sub-commands specified in the second process and the first destination chip of the currently executed first sub-command;
• when the second destination chip specified in the second process is same as the first destination chip of the currently executed first sub-command queue each of the second sub-commands in the set of second sub-commands into the first command queue that is empty;
• and
• when the second destination chip specified in the second process is different from the first destination chip of the currently executed first sub-command, queue a head second sub-command in the set of second sub-commands into the second command queue that is empty, and queue other second sub-commands than the head second sub-command in the set of second sub-commands into the first command queue that is empty.