Cache buffer and semiconductor memory device having the same

A memory device comprising:

• a memory cell array including a plurality of memory cells;
• a page buffer configured to perform a program operation or read operation on the memory cell array;
• and
• a cache buffer coupled to the page buffer,
• wherein the cache buffer includes:
• a first cache group corresponding to a first area of the memory cell array;
• a second cache group corresponding to a second area of the memory cell array;
• a selector coupled to the first cache group and the second cache group;
• and
• an input/output (I/O) controller coupled to the selector and configured to output data to the first cache group and the second cache group or receive data input from the first cache group and the second cache group,
• wherein the selector:
• performs normal repair operation by transferring data received through a first data line to the first cache group and transferring data received through a second data line to the second cache group;
• and
• performs cross repair operation by transferring data received through the first data line to the second cache group and transferring data received through the second data line to the first cache group.

A cache buffer coupled to a memory cell array, the cache buffer comprising:

• a main cache unit configured to cache data of a main memory area within the memory cell array;
• a first repair cache unit configured to cache data of a first repair memory area within the memory cell array;
• a second repair cache unit configured to cache data of a second repair memory area within the memory cell array;
• and
• an I/O control component configured to:
• transfer, when the main memory area is available, data through a first path between the main cache unit and an external entity;
• change the first path to a second path between the first repair cache unit and the external entity during a normal repair operation performed to repair the main memory area with the first repair memory area;
• and
• change the first path to a third path between the second repair cache unit and the external entity during a cross repair operation performed to repair the main memory area with the second repair memory area.