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US 10,761,747 B2Granted
Memory device and memory system including the same
AssigneeSK hynix Inc.
InventorsDo-Sun Hong, Jung Hyun Kwon, Seung Gyu Jeong, Won Gyu Shin
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory region; and an access unit suitable for setting an offset value according to control of an external device, changing, in response to an access command of the external device for a first address of the memory region, the first address into a second address of the memory region based on the offset value, and performing an access operation for the second address.
Claims17
A memory system comprising:
- a first memory device;
- a second memory device;
- and
- a controller coupled with the first memory device and the second memory device through a control line and an offset value setting line, and coupled with the first memory device and the second memory device through a first data line and a second data line, respectively,
- wherein the controller transmits a write command to the first memory device and the second memory device through the control line and transmits the first offset value and the second offset value to the first memory device and the second memory device through the first data line and the second data line, respectively, while activating the offset value setting line, and then transmits an access command for a first address to the first memory device and the second memory device through the control line,
- wherein the first memory device sets the first offset value in response to the write command, and changes the first address based on the first offset value in response to the access command
- wherein the second memory device sets the second offset value in response to the write command, and changes the first address based on the second offset value in response to the access command.
4 more elements
A memory system comprising:
- first memory device including a first memory unit corresponding to a first target address;
- second memory device including a second memory unit corresponding to a second target address;
- and
- a controller suitable for determining whether to perform a management operation for the first and second target addresses based on a write count for a reference address in the first and second memory devices, and simultaneously accessing the first and second memory units when performing the management operation.
1 more element
Dependencies are inferred from the claim text.