Programmable power management agent

A processor comprising:

• at least one core including a first core;
• a power management agent (PMA) coupled to the first core, the PMA comprising:
• a static table to store a list of operations, the static table comprising a plurality of columns, each column to specify a corresponding flow, each flow to include a corresponding subset of the operations and each flow associated with a corresponding state of the first core;
• a control register (CR) comprising a plurality of storage elements, wherein each storage element corresponds to a respective operation listed in the static table, each storage element to receive one of a first value and a second value;
• and
• execution logic, responsive to a command to place the first core into a first state, to execute each operation of a first flow for which the corresponding storage element stores the first value and to refrain from execution of each operation of the first flow for which the corresponding element stores the second value;
• and
• a power controller coupled to the first core via a first interconnect, the power controller to determine a corresponding value to be stored in each of the storage elements of the CR.

A system comprising:

• a processor comprising:
• at least one core including a first core;
• a power management agent (PMA) coupled to the first core, the PMA comprising:
• a static table to store a list of operations, the static table comprising a plurality of columns, each column to specify a corresponding flow, each flow to include a corresponding subset of the operations and each flow associated with a corresponding state of the first core;
• a control register (CR) comprising a plurality of storage elements, wherein each storage element corresponds to a respective operation listed in the static table, each storage element to receive one of a first value and a second value;
• and
• execution logic, responsive to a command to place the first core into a first state, to execute each operation of a first flow for which the corresponding storage element stores the first value and to refrain from execution of each operation of the first flow for which the corresponding element stores the second value;
• and
• a power controller coupled to the first core via a first interconnect, the power controller to determine a corresponding value to be stored in each of the storage elements of the CR;
• and
• a system memory coupled to the processor.