Interconnect fabric link width reduction to reduce instantaneous power consumption

A parallel processor comprising:

• a first processing cluster including a first interface node, the first interface node having a first ingress module and a first egress module, wherein connection links of the first ingress module are separate from the connection links of the first egress module;
• and
• an interconnect fabric coupled with the first interface node of the first processing cluster, the interconnect fabric including a dynamic bus module to dynamically configure active bus widths for connections to the first interface node, wherein the dynamic bus module is to dynamically configure a first active bus width for the first ingress module based on a first rate of data transfer requests through the first interface node and dynamically configure a second active bus width for the first egress module based on a second rate of data transfer requests through the first interface node, the first active bus width different from the second active bus width.