Error checking for primary signal transmitted between first and second clock domains

A method for transmitting a primary signal between a first portion operating in a first clock domain and a second portion operating in a second clock domain, the method comprising:

• receiving a primary signal at a first primary interface on the first portion, and receiving a first checking signal at a first redundant interface on the first portion, the first checking signal and the primary signal being separated by a predetermined time delay;
• outputting the primary signal at a second primary interface on the second portion, and outputting a second checking signal at a second redundant interface on the second portion;
• wherein checking circuitry in the second clock domain is configured to:
• generate the second checking signal based on the primary signal;
• perform an error checking procedure based on the first and second checking signals;
• and
• supply the second checking signal to the second redundant interface said predetermined time delay after the primary signal is supplied to the second primary interface.

A computer-implemented method of generating an electronic design file representing a design of an interconnection network for providing data transfer between a plurality of nodes of an integrated circuit;

• the method comprising:
• in response to identifying that the plurality of nodes include a first node operating in a first clock domain and a second node operating in a second clock domain, generating the electronic design file specifying that the interconnection network comprises a clock domain crossing comprising:
• a first portion operating in the first clock domain and a second portion operating in the second clock domain;
• wherein the first portion comprises a first primary interface and a first redundant interface, the first primary interface being configured to receive a primary signal, and the first redundant interface being configured to receive a first checking signal, the first checking signal and the primary signal being separated by a predetermined time delay;
• and
• wherein the second portion comprises a second primary interface and a second redundant interface, the second primary interface being configured to output the primary signal, and the second redundant interface being configured to output a second checking signal;
• the apparatus comprising checking circuitry in the second clock domain configured to:
• generate the second checking signal based on the primary signal;
• perform an error checking procedure based on the first and second checking signals;
• and
• supply the second checking signal to the second redundant interface said predetermined time delay after the primary signal is supplied to the second primary interface.