Clock gating enable generation
AssigneeQUALCOMM Incorporated
InventorAdam Andrew Zerwick
Life of this patent
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Abstract
In one embodiment, a clock-gating system for a pipeline includes a clock-gating device configured to gate or pass a clock signal to the pipeline, and a clock controller. The clock controller is configured to track a number of input packets at an input of the pipeline, to track a number of output packets at an output of the pipeline, to determine whether to gate or pass the clock signal based on the number of the input packets and the number of the output packets, to instruct the clock-gating device to pass the clock signal if a determination is made to pass the clock signal, and to instruct the clock-gating device to gate the clock signal if a determination is made to gate the clock signal.
Claims20
A clock-gating system for a multi-stage pipeline, comprising:
- a clock-gating device configured to pass or gate a clock signal to the multi-stage pipeline;
- and
- a clock controller configured to track a number of input packets at at least a single input of the multi-stage pipeline, to track a number of output packets at at least a single output of the multi-stage pipeline, to determine whether to pass or gate the clock signal based on the number of the input packets at the at least single input of the multi-stage pipeline and the number of the output packets at the at least single output of the multi-stage pipeline, to instruct the clock-gating device to pass the clock signal if a determination is made to pass the clock signal, and to instruct the clock-gating device to gate the clock signal if a determination is made to gate the clock signal.
A method for clock gating, comprising:
- tracking a number of input packets at at least a single input of a multi-stage pipeline;
- tracking a number of output packets at at at least a single output of the multi-stage pipeline;
- determining whether to gate or pass a clock signal to the multi-stage pipeline based on the number of the input packets at the at least single input of the multi-stage pipeline and the number of the output packets at the at least single output of the multi-stage pipeline;
- passing the clock signal to the multi-stage pipeline if a determination is made to pass the clock signal;
- and
- gating the clock signal if a determination is made to gate the clock signal.
Dependencies are inferred from the claim text.