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US 10,761,384 B2Granted
Electro-optical device and electronic apparatus
AssigneeSeiko Epson Corporation
InventorsShotaro Izawa, Satoshi Ito
Life of this patent
Estimating the term…
Abstract
On the first side substrate of an electro-optical device, a first maintenance capacitance is formed by a first capacitance electrode, a first dielectric layer, and a second capacitance electrode overlapped with each other on a bottom and an inner walls of a first recess section formed in an inter-layer insulation film. The inter-layer insulation film needs to be thick and thus an inter-layer insulation film needs to be thin. A first capacitance line is formed on a surface of the inter-layer insulation film on the side of a pixel electrode. Thus, the first capacitance line shields a section between a gate electrode and the second capacitance electrode to which a drain potential is applied.
Claims8
An electro-optical device comprising:
- a first side substrate provided with a pixel electrode on one side of a first substrate;
- a second side substrate, provided with a common electrode to which a common potential is applied on a surface of a second substrate on a side of the first side substrate, the second substrate facing the first side substrate;
- and
- an electro-optical layer arranged between the first side substrate and the second side substrate, wherein
- the first side substrate includes
- a pixel transistor including:
- a semiconductor layer arranged between the first substrate and the pixel electrode;
- a gate electrode arranged on a side of the pixel electrode with respect to the semiconductor layer;
- a source electrode arranged between the pixel electrode and the semiconductor layer, and electrically coupled to a source region of the semiconductor layer;
- and
- a drain electrode arranged between the pixel electrode and the semiconductor layer, and electrically coupled to a drain region of the semiconductor layer,
- a first scan line extending in a first direction and electrically coupled to the gate electrode,
- a data line, between the semiconductor layer and the pixel electrode, extending in a second direction intersecting the first direction, and electrically coupled to the source electrode,
- a first inter-layer insulation film covering the gate electrode from a side of the pixel electrode,
- a first capacitance line to which the common potential is applied, the first capacitance line extending on a surface of the first inter-layer insulation film on the side of the pixel electrode to overlap with the gate electrode in a plan view,
- a second inter-layer insulation film covering the first capacitance line from the side of the pixel electrode, and including a first recess section that overlaps with the first capacitance line in a plan view,
- a first capacitance electrode arranged from a bottom of the first recess section to a surface of the second inter-layer insulation film on the side of the pixel electrode, and electrically coupled to the first capacitance line at the bottom of the first recess section,
- a second capacitance electrode overlapping with the first capacitance electrode from the side of the pixel electrode and electrically coupled to the drain electrode and the pixel electrode,
- a first dielectric layer, arranged between the first capacitance electrode and the second capacitance electrode, for constituting, with the first capacitance electrode and the second capacitance electrode, a first holding capacitance,
- a second capacitance line to which the common potential is applied, the second capacitance line extending between the second capacitance electrode and the pixel electrode,
- a third inter-layer insulation film covering the second capacitance line from the side of the pixel electrode, and including a second recess section that overlaps with the second capacitance line in a plan view,
- a third capacitance electrode arranged from a bottom of the second recess section to a surface of the third inter-layer insulation film on the side of the pixel electrode, and electrically coupled to the second capacitance line at the bottom of the second recess section,
- a fourth capacitance electrode overlapping with the second capacitance electrode from the side of the pixel electrode, and electrically coupled to the drain electrode and the pixel electrode, and
- a second dielectric layer, arranged between the third capacitance electrode and the fourth capacitance electrode, for constituting, with the third capacitance electrode and the fourth capacitance electrode, a second holding capacitance.
21 more elements
An electro-optical device comprising:
- a first side substrate provided with a pixel electrode on one side of a first substrate,
- a second side substrate, provided with a common electrode to which a common potential is applied on a surface of a second substrate on a side of the first side substrate, the second substrate facing the first side substrate, and
- an electro-optical layer arranged between the first side substrate and the second side substrate, wherein
- the first side substrate includes
- a pixel transistor including:
- a semiconductor layer arranged between the first substrate and the pixel electrode;
- a gate electrode arranged on a side of the pixel electrode with respect to the semiconductor layer;
- a source electrode arranged between the pixel electrode and the semiconductor layer, and electrically coupled to a source region of the semiconductor layer;
- and
- a drain electrode arranged between the pixel electrode and the semiconductor layer, and electrically coupled to a drain region of the semiconductor layer,
- a first scan line extending in a first direction and electrically coupled to the gate electrode,
- a data line, between the semiconductor layer and the pixel electrode, extending in a second direction intersecting the first direction, and electrically coupled to the source electrode,
- a first inter-layer insulation film covering the gate electrode from a side of the pixel electrode,
- a first capacitance line to which the common potential is applied, the first capacitance line extending on a surface of the first inter-layer insulation film on the side of the pixel electrode to overlap with the gate electrode in a plan view,
- a second inter-layer insulation film covering the first capacitance line from the side of the pixel electrode, and including a first recess section that overlaps with the first capacitance line in a plan view,
- a first capacitance electrode arranged from a bottom of the first recess section to a surface of the second inter-layer insulation film on the side of the pixel electrode, and electrically coupled to the first capacitance line at the bottom of the first recess section,
- a second capacitance electrode overlapping with the first capacitance electrode from the side of the pixel electrode and electrically coupled to the drain electrode and the pixel electrode,
- a first dielectric layer, arranged between the first capacitance electrode and the second capacitance electrode, for constituting, with the first capacitance electrode and the second capacitance electrode, a first holding capacitance,
- the first scan line extends in the first direction between the semiconductor layer and the first inter-layer insulation film,
- the first capacitance line extends in the first direction to overlap with the first scan line in a plan view,
- a second scan line extending in the first direction to overlap with the first scan line, between the first substrate and the semiconductor layer, and
- a fourth inter-layer insulation film arranged between the semiconductor layer and the second scan line, and
- the first scan line is electrically coupled to the second scan line through a first contact hole formed through the fourth inter-layer insulation film.
20 more elements
An electro-optical device comprising:
- a first side substrate provided with a pixel electrode on one side of a first substrate;
- a second side substrate, provided with a common electrode to which a common potential is applied on a surface of a second substrate on a side of the first side substrate, the second substrate facing the first side substrate;
- and
- an electro-optical layer arranged between the first side substrate and the second side substrate, wherein
- the first side substrate includes
- a pixel transistor including:
- a semiconductor layer arranged between the first substrate and the pixel electrode;
- a gate electrode arranged on a side of the pixel electrode with respect to the semiconductor layer;
- a source electrode arranged between the pixel electrode and the semiconductor layer, and electrically coupled to a source region of the semiconductor layer, and
- a drain electrode arranged between the pixel electrode and the semiconductor layer, and electrically coupled to a drain region of the semiconductor layer,
- a first scan line extending in a first direction and electrically coupled to the gate electrode,
- a data line, between the semiconductor layer and the pixel electrode, extending in a second direction intersecting the first direction, and electrically coupled to the source electrode,
- a first inter-layer insulation film covering the gate electrode from a side of the pixel electrode,
- a first capacitance line to which the common potential is applied, the first capacitance line extending on a surface of the first inter-layer insulation film on the side of the pixel electrode to overlap with the gate electrode in a plan view,
- a second inter-layer insulation film covering the first capacitance line from t e side of the pixel electrode, and including a first recess section that overlaps with the first capacitance line in a plan view,
- a first capacitance electrode arranged from a bottom of the first recess section to a surface of the second inter-layer insulation film on the side of the pixel electrode, and electrically coupled to the first capacitance line at the bottom of the first recess section,
- a second capacitance electrode overlapping with the first capacitance electrode from the side of the pixel electrode and electrically coupled to the drain electrode and the pixel electrode, and
- a first dielectric layer, arranged between the first capacitance electrode and the second capacitance electrode, for constituting, with the first capacitance electrode and the second capacitance electrode, a first holding capacitance,
- the first inter-layer insulation film includes
- a fifth inter-layer insulation film arranged between the semiconductor layer and the first capacitance line, and
- a sixth inter-layer insulation film arranged between the fifth inter-layer insulation film and the first capacitance line,
- the gate electrode is arranged between the fifth inter-layer insulation film in the first inter-layer insulation film and the semiconductor layer,
- the first scan line is arranged between the fifth inter-layer insulation film and the sixth inter-layer insulation film in the first inter-layer insulation film, and
- a second contact hole through which the first scan line and the gate electrode are electrically coupled is formed in the fifth inter-layer insulation film.
21 more elements
Dependencies are inferred from the claim text.