Semiconductor apparatus and diagnostic test method
AssigneeRenesas Electronics Corporation
InventorsShinichi Shibahara, Daisuke Kawakami, Yutaka Igaku
Life of this patent
Estimating the term…
Abstract
A semiconductor apparatus includes a storage circuit, a processing circuit that performs processing using data stored in the storage circuit and writes data into the storage circuit as the processing is performed, a scan test circuit that executes a scan test on the processing circuit when the processing circuit does not perform processing, and an inhibit circuit that inhibits writing of data from the processing circuit to the storage circuit when the scan test on the processing circuit is executed.
Claims20
A semiconductor apparatus comprising:
- an arithmetic circuit;
- a common circuit comprising a storage circuit configured to hold data used for performing processing by the arithmetic circuit, a controller configured to control access to the storage circuit, and an inhibit circuit;
- a reset controller configured to reset the common circuit;
- and
- a scan test circuit configured to execute a scan test on the common circuit when the arithmetic circuit does not perform the processing;
- wherein the inhibit circuit inhibits the controller from writing of data to the storage circuit for initialization of data held in the storage circuit when the reset controller resets the common circuit after execution of the scan test on the common circuit.
A semiconductor apparatus comprising:
- a storage circuit;
- a processing circuit that performs processing using data stored in the storage circuit and writes data into the storage circuit as the processing is performed;
- a scan test circuit that executes a scan test on the processing circuit;
- an inhibit circuit;
- and
- a reset controller that resets the processing circuit after execution of the scan test on the processing circuit,
- wherein the processing circuit performs initialization of data in the storage circuit when the processing circuit is reset,
- wherein the inhibit circuit is configured to inhibit the processing circuit from performing initialization of data in the storage circuit when the processing circuit is reset after execution of the scan test.
A diagnostic test method comprising:
- performing processing using data stored in a storage circuit and, when a processing circuit that writes data into the storage circuit as the processing is performed does rot perform processing, executing a scan test on the processing circuit;
- resetting the processing circuit after execution of the scan test on the processing circuit;
- and
- inhibiting the processing circuit from performing initialization of data in the storage circuit when the processing circuit is reset after execution of the scan test,
- wherein the performing step comprises initialization of data in the storage circuit when the processing circuit is reset,
- the method further comprising, when the processing circuit is reset after execution of the scan test, inhibiting the processing circuit from performing initialization of data in the storage circuit, thereby maintaining content of the storage circuit after the end of the scan test.
Dependencies are inferred from the claim text.