Architecture flexible binary arithmetic coding system
AssigneeAvago Technologies International Sales Pte. Limited
InventorMinhua Zhou
Life of this patent
Estimating the term…
Abstract
In the subject architecture flexible binary arithmetic coding system, coding circuitry of an electronic device may receive video data that is to be coded (e.g., to be encoded or decoded) by binary arithmetic coding. The coding circuitry may also compute at least one of a least probable symbol (LPS) range or a most probable symbol (MPS) range based on a multiplication operation (e.g., without performing a table look-up operation). The coding circuitry may perform binary arithmetic coding on the video data using the at least one of the LPS range or the MPS range. The computation of the LPS range and/or the MPS range using the multiplication operation may have a lower computational cost than using a table look-up operation.
Claims20
A device, comprising:
- at least one processor configured to:
- receive video data;
- compute at least one of a least probable symbol (LPS) range or a most probable symbol (MPS) range based on a multiplication operation by shifting a multiplication result from the multiplication operation by a third shift bit number, the third shift bit number being calculated by subtracting a first shift bit number and a second shift bit number from a storage precision of a probability state;
- and
- perform binary arithmetic coding on the video data using the at least one of the LPS range or the MPS range,
- wherein the multiplication operation includes multiplication of a quantized compound range and a storage precision based value based on a quantized probability state, and
- wherein the quantized compound range is quantized by the first shift bit number and the quantized probability state is quantized by the second shift bit number.
A method performed by a device, comprising:
- receiving video data;
- computing at least one of a least probable symbol (LPS) range or a most probable symbol (MPS) range based on a multiplication operation by shifting a multiplication result from the multiplication operation by a third shift bit number, the third shift bit number being calculated by subtracting a first shift bit number and a second shift bit number from a storage precision of a probability state;
- and
- performing binary arithmetic coding on the video data using the at least one of the LPS range or the MPS range,
- wherein the multiplication operation includes multiplication of a quantized compound range and a storage precision based value based on a quantized probability state, and
- wherein the quantized compound range is quantized by the first shift bit number and the quantized probability state is quantized by the second shift bit number.
A non-transitory, processor-readable storage media encoded with instructions that, when executed by processor, perform a method comprising:
- receiving video data;
- computing at least one of a least probable symbol (LPS) range or a most probable symbol (MPS) range based on a multiplication operation;
- and
- performing binary arithmetic coding the video data using the at least one of the LPS range or the MPS range by shifting a multiplication result from the multiplication operation by a third shift bit number, the third shift bit number being calculated by subtracting a first shift bit number and a second shift bit number from a storage precision of a probability state,
- wherein the multiplication operation includes multiplication of a quantized compound range and a storage precision based value based on a quantized probability state, and
- wherein the quantized compound range is quantized by the first shift bit number and the quantized probability state is quantized by the second shift bit number.
Dependencies are inferred from the claim text.