Comparison device and CMOS image sensor including the same

A device comprising:

• a comparison circuit configured to compare an input signal with a ramp signal and to output a comparison signal;
• a banding noise adjustment circuit coupled to the comparison circuit to adjust electrical characteristic values of the comparison circuit;
• a banding value generation circuit coupled to the banding noise adjustment circuit to provide the banding noise adjustment circuit with a banding value based on a setting code value;
• and
• a banding noise reduction circuit coupled to the banding noise adjustment circuit and configured to reduce the banding noise of the comparison circuit based on adjustment of the electrical characteristic values of the comparison circuit,
• wherein the banding value generation circuit generates a banding noise control voltage corresponding to the setting code value, and applies the banding noise control voltage to the banding noise adjustment circuit of each column,
• wherein the banding value generation circuit comprises:
• a storage circuit configured to store the setting code value;
• a voltage generation circuit coupled to the storage circuit to receive the setting code value and configured to generate the banding noise control voltage corresponding to the setting code value output from the storage circuit;
• and
• a voltage transfer circuit coupled to the voltage generation circuit and configured to transfer the banding noise control voltage to the banding noise adjustment circuit.

A device having a CMOS image sensor which comprises:

• a pixel array including a plurality of imaging pixels arranged in rows and columns to output a pixel signal corresponding to incident light;
• a row decoder coupled to the pixel array to select and control the plurality of imaging pixels in the pixel array by selecting row lines;
• a ramp signal generator configured to generate a ramp signal;
• a comparison circuit configured to compare each pixel signal of the pixel array with the ramp signal of the ramp signal generator;
• a banding noise adjustment circuit coupled to the comparison circuit to offset a banding noise of the comparison circuit by adjusting electrical characteristic values of the comparison circuit;
• a banding value generation circuit coupled to the banding noise adjustment circuit to provide the banding noise adjustment circuit with a banding value generated based on a setting code value;
• a banding noise reduction circuit coupled to the banding noise adjustment circuit and configured to reduce the banding noise of the comparison circuit by adjusting electrical characteristic values of the comparison circuit;
• a counting circuit coupled to the comparison circuit to count a number of clock pulses according to each output signal of the comparison circuit;
• a memory circuit coupled to the counting circuit to store information provided by the counting circuit;
• a control circuit configured to provide instructions to the row decoder, the ramp signal generator, the comparison circuit, the counting circuit, and the memory circuit;
• and
• a column readout circuit configured to output data of the memory circuit based on the instructions provided by the control circuit.