US 10,756,095 B2Granted

SRAM cell with T-shaped contact

AssigneeTexas Instruments Incorporated

InventorsTheodore W. Houston, Thomas J. Aton, Scott W. Jessen

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Abstract

An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.

Claims20

Dependent claims

An integrated circuit containing an array of Static Random Access Memory (SRAM) cells, each said SRAM cell comprising:

a first driver transistor of said SRAM cell of said array within said integrated circuit, said first driver transistor having a drain node and a channel region;
a first load transistor, said first load transistor having a drain node and a channel region;
a first inverter gate, said first inverter gate overlapping said channel region of said first driver transistor and overlapping said channel region of said first load transistor;
a second driver transistor, said second driver transistor having a drain node and a channel region;
a second load transistor, said second load transistor having a drain node and a channel region;
a second inverter gate, said second inverter gate overlapping said channel region of said second driver transistor and overlapping said channel region of said second load transistor;
a first T-shaped contact, further including:
a first drain connecting segment, said first drain connecting segment overlapping said drain node of said first driver transistor and overlapping said drain node of said first load transistor;
and
a first gate connecting segment located substantially laterally adjacent to said first drain connecting segment, said first gate connecting segment overlapping said second inverter gate and intersecting said first drain connecting segment;
a second T-shaped contact, further including:
a second drain connecting segment, said second drain connecting segment overlapping said drain node of said second driver transistor and overlapping said drain node of said second load transistor;
and
a second gate connecting segment located substantially laterally adjacent to said second drain connecting segment, said second gate connecting segment overlapping said first inverter gate and intersecting said second drain connecting segment;
an end of said first gate connecting segment overlapping said second inverter gate is inclined toward an end of said first drain connecting segment overlapping said drain node of said first load transistor by a first inclined distance, said first inclined distance being greater than half a distance by which said end of said first drain connecting segment extends beyond said first gate connecting segment;
and
an end of said second gate connecting segment overlapping said first inverter gate is inclined toward an end of said second drain connecting segment overlapping said drain node of said second load transistor by a second inclined distance, said second inclined distance being greater than half a distance by which said end of said second drain connecting segment extends beyond said second gate connecting segment.

14 more elements

An integrated circuit containing an array of Static Random Access Memory (SRAM) cells, each said SRAM cell comprising:

a first driver transistor of said SRAM cell of said array within said integrated circuit, said first driver transistor having a drain node and a channel region;
a first load transistor, said first load transistor having a drain node and a channel region;
a first inverter gate, said first inverter gate overlapping said channel region of said first driver transistor and overlapping said channel region of said first load transistor;
a second driver transistor, said second driver transistor having a drain node and a channel region;
a second load transistor, said second load transistor having a drain node and a channel region;
a second inverter gate, said second inverter gate overlapping said channel region of said second driver transistor and overlapping said channel region of said second load transistor;
a first T-shaped contact, further including:
a first drain connecting segment, said first drain connecting segment overlapping said drain node of said first driver transistor and overlapping said drain node of said first load transistor;
and
a first gate connecting segment located substantially laterally adjacent to said first drain connecting segment, said first gate connecting segment overlapping said second inverter gate and intersecting said first drain connecting segment;
a second T-shaped contact, further including:
a second drain connecting segment, said second drain connecting segment overlapping said drain node of said second driver transistor and overlapping said drain node of said second load transistor;
and
a second gate connecting segment located substantially laterally adjacent to said second drain connecting segment, said second gate connecting segment overlapping said first inverter gate and intersecting said second drain connecting segment;
an end of said first gate connecting segment overlapping said second inverter gate is inclined toward an end of said first drain connecting segment overlapping said drain node of said first load transistor by a first inclined distance, said first inclined distance being greater than half a distance by which said end of said first drain connecting segment extends beyond said first gate connecting segment.

12 more elements

An integrated circuit containing an array of Static Random Access Memory (SRAM) cells, each said SRAM cell comprising:

a first driver transistor of said SRAM cell of said array within said integrated circuit, said first driver transistor having a drain node and a channel region;
a first load transistor, said first load transistor having a drain node and a channel region;
a first inverter gate, said first inverter gate overlapping said channel region of said first driver transistor and overlapping said channel region of said first load transistor;
a second driver transistor, said second driver transistor having a drain node and a channel region;
a second load transistor, said second load transistor having a drain node and a channel region;
a second inverter gate, said second inverter gate overlapping said channel region of said second driver transistor and overlapping said channel region of said second load transistor;
a first T-shaped contact, further including:
a first drain connecting segment, said first drain connecting segment overlapping said drain node of said first driver transistor and overlapping said drain node of said first load transistor;
and
a first gate connecting segment located substantially laterally adjacent to said first drain connecting segment, said first gate connecting segment overlapping said second inverter gate and intersecting said first drain connecting segment;
a second T-shaped contact, further including:
a second drain connecting segment, said second drain connecting segment overlapping said drain node of said second driver transistor and overlapping said drain node of said second load transistor;
and
a second gate connecting segment located substantially laterally adjacent to said second drain connecting segment, said second gate connecting segment overlapping said first inverter gate and intersecting said second drain connecting segment;
an end of said second gate connecting segment overlapping said first inverter gate is inclined toward an end of said second drain connecting segment overlapping said drain node of said second load transistor by a second inclined distance, said second inclined distance being greater than half a distance by which said end of said second drain connecting segment extends beyond said second gate connecting segment.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/188,718Filed 13 Nov 2018 · continuation
Priority: 5 Jun 2009
Published: US 2019/0081051 A114 Mar 2019
Granted: 25 Aug 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
H10B 10/00
Static random access memory [sram] devices
H10D 84/0149
The components including insulated gates, e.g. IGFETs: manufacturing their interconnections or electrodes, e.g. source or drain electrodes
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe

Family

Application12/479,266Parent of this continuation · filed 5 Jun 2009
US 2019/0081051 A1Pre-grant publication · published 14 Mar 2019
US 10,163,911 B2Parent of this continuation
US 2010/0308419 A1Published application
US 10,756,095 B2This patent

From the US filing history. Foreign family members aren’t listed.