Energy efficient processor core architecture for image processor
AssigneeGoogle Inc.
InventorsAlbert Meixner, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu
Life of this patent
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Abstract
An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.
Claims20
A computing device comprising:
- an array of execution lanes;
- a scalar lane;
- a two-dimensional shift-register array;
- and
- a sheet generator configured to load sheets of data into the two-dimensional shift register array, wherein the computing device is configured to perform operations comprising:
- receiving, by the scalar lane, an instruction specifying an operation to be performed using an operand having a first bit width, wherein the first bit width is wider than a second bit width of shift registers in the shift-register array;
- issuing one or more instructions to the sheet generator that cause the sheet generator to load a high sheet and a low sheet into the shift-register array of the computing device;
- and
- providing, by the scalar lane to each of the execution lanes in the execution lane array, one or more instructions to perform the operation using the operand having the first bit width using data from the high sheet and the low sheet loaded into the shift-register array.
A method performed by computing device having an array of execution lanes, a scalar lane, a two-dimensional shift-register array, and a sheet generator configured to load sheets of data into the two-dimensional shift-register array, the method comprising:
- receiving, by the scalar lane, an instruction specifying an operation to be performed using an operand having a first bit width, wherein the first bit width is wider than a second bit width of shift registers in the shift-register array;
- issuing one or more instructions to the sheet generator that cause the sheet generator to load a high sheet and a low sheet into the shift-register array of the computing device;
- and
- providing, by the scalar lane to each of the execution lanes in the execution lane array, one or more instructions to perform the operation using the operand having the first bit width using data from the high sheet and the low sheet loaded into the shift-register array.
One or more non-transitory computer storage media encoded with instructions to be executed by a computing device comprising an array of execution lanes, a scalar lane, a two-dimensional shift-register array, and a sheet generator configured to load sheets of data into the two-dimensional shift register array,
- wherein the instructions comprise an instruction specifying an operation to be performed using an operand having a first bit width, wherein the first bit width is wider than a second bit width of shift registers in the shift-register array, and wherein executing the instruction causes the computing device to perform operations comprising:
- issuing one or more instructions to the sheet generator that cause the sheet generator to load a high sheet and a low sheet into the shift-register array of the computing device;
- and
- providing, by the scalar lane to each of the execution lanes in the execution lane array, one or more instructions to perform the operation using the operand having the first bit width using data from the high sheet and the low sheet loaded into the shift-register array.
Dependencies are inferred from the claim text.