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US 10,754,616 B1Granted
Processing with compact arithmetic processing element
AssigneeSingular Computing LLC
InventorJoseph Bates
Life of this patent
Estimating the term…
Abstract
Low precision computers can be efficient at finding possible answers to search problems. However, sometimes the task demands finding better answers than a single low precision search. A computer system augments low precision computing with a small amount of high precision computing, to improve search quality with little additional computing.
Claims25
A computing system, comprising:
- a host computer;
- a computing chip comprising:
- a processing element array comprising a first edge processing element positioned at a first edge of the processing element array, a second edge processing element positioned at the first edge of the processing element array, a first interior processing element positioned at a first location in an interior of the processing element array, and a second interior processing element positioned at a second location in the interior of the processing element array;
- a first processing element connection connecting the first edge processing element with the first interior processing element;
- a second processing element connection connecting the second edge processing element with the second interior processing element;
- an input-output unit connected to the first edge processing element and the second edge processing element;
- a first memory local to the first edge processing element;
- a second memory local to the second edge processing element;
- a third memory local to the first interior processing element;
- and,
- a fourth memory local to the second interior processing element;
- wherein the first edge processing element comprises a first arithmetic unit;
- wherein the second edge processing element comprises a second arithmetic unit;
- wherein the first interior processing element comprises a third arithmetic unit;
- and
- wherein the second interior processing element comprises a fourth arithmetic unit;
- and,
- a host connection at least partially connecting the input-output unit with the host computer;
- wherein the first, second, third and fourth arithmetic units each comprises a corresponding multiplier circuit adapted to receive as a first input to the corresponding multiplier circuit a first floating point value having a first binary mantissa of width no more than 11 bits and a first binary exponent of width at least 6 bits, and to receive as a second input to the corresponding multiplier circuit a second floating point value having a second binary mantissa of width no more than 11 bits and a second binary exponent of width at least 6 bits.
16 more elements
A computing system, comprising:
- a host computer;
- a computing chip comprising:
- a processing element array comprising a plurality of first processing elements, wherein the plurality of first processing elements is no less than 5000 in number, wherein each of a first subset of the plurality of first processing elements is positioned at a first edge of the processing element array, and wherein each of a second subset of the plurality of first processing elements is positioned in the interior of the processing element array;
- an input-output unit connected to each of the first subset of the plurality of first processing elements;
- a plurality of processing element connections, each processing element connection connecting one of the plurality of first processing elements with another of the plurality of first processing elements, wherein each of the plurality of first processing elements is connected to at least one other of the plurality of first processing elements by at least one of the plurality of processing element connections;
- a plurality of memory units, wherein each of the plurality of first processing elements is associated with a corresponding one of the plurality of memory units, and wherein each of the plurality of memory units is local to its associated one of the plurality of first processing elements;
- and,
- a plurality of arithmetic units, wherein each of the plurality of first processing elements has positioned therein at least one of the plurality of arithmetic units;
- and,
- a host connection at least partially connecting the input-output unit with the host computer;
- wherein the plurality of arithmetic units each comprises a first corresponding multiplier circuit adapted to receive as a first input to the first corresponding multiplier circuit a first floating point value having a first binary mantissa of width no more than 11 bits and a first binary exponent of width at least 6 bits, and to receive as a second input to the first corresponding multiplier circuit a second floating point value having a second binary mantissa of width no more than 11 bits and a second binary exponent of width at least 6 bits.
8 more elements
A computing system, comprising:
- a host computer;
- a computing chip comprising:
- a processing element array comprising a first edge processing element positioned at a first edge of the processing element array, a second edge processing element positioned at the first edge of the processing element array, a first interior processing element positioned at a first location in the interior of the processing element array, and a second interior processing element positioned at a second location in the interior of the processing element array;
- a first processing element connection connecting the first edge processing element with the first interior processing element;
- a second processing element connection connecting the second edge processing element with the second interior processing element;
- an input-output unit connected to the first edge processing element and the second edge processing element;
- a first memory local to the first edge processing element;
- a second memory local to the second edge processing element;
- a third memory local to the first interior processing element;
- and
- a fourth memory local to the second interior processing element;
- wherein the first edge processing element comprises a first arithmetic unit;
- wherein the second edge processing element comprises a second arithmetic unit;
- wherein the first interior processing element comprises a third arithmetic unit;
- and
- wherein the second interior processing element comprises a fourth arithmetic unit;
- a host connection at least partially connecting the input-output unit with the host computer;
- an external edge processing element external to the computing chip;
- an external input-output unit external to the computing chip;
- and,
- a fifth memory local to the external edge processing element;
- wherein the external edge processing element comprises a fifth arithmetic unit;
- wherein the first, second, third, fourth, and fifth arithmetic units each comprises a first corresponding multiplier circuit adapted to receive as a first input to the first corresponding multiplier circuit a first floating point value having a first binary mantissa of width no more than 11 bits and a first binary exponent of width at least 6 bits, and to receive as a second input to the first corresponding multiplier circuit a second floating point value having a second binary mantissa of width no more than 11 bits and a second binary exponent of width at least 6 bits;
- and
- wherein the first edge processing element is connected with the external edge processing element through the input-output unit and the external input-output unit.
22 more elements
Dependencies are inferred from the claim text.