Semiconductor device

A semiconductor device, comprising:

• a function cell designed using a basic cell including a first wiring layer provided over a main surface of a semiconductor substrate and having a predetermined pattern and a second wiring layer provided over the first wiring layer and having a predetermined pattern, the function cell corresponding to the basic cell which is modified to have a predetermined function by changing the pattern of the second wiring layer at a design stage,
• wherein the function cell has a first layout and a second layout which are disposed in juxtaposition in one direction in a plane parallel with the main surface,
• wherein the function cell is provided with the predetermined function by coupling together wires belonging to the respective second wiring layers of the first layout and the second layout,
• wherein the first layout includes:
• two first transistors having a first conductivity type and one shared diffusion layer;
• two second transistors disposed in juxtaposition with the two first transistors in another direction crossing the one direction in the plane and having a second conductivity type and one shared diffusion layer;
• a first wire coupling the other diffusion layer of each of the first transistors to a first power supply;
• a second wire coupled to the shared one diffusion layer of the first transistors;
• a third wire coupling the other diffusion layer of each of the second transistors to a second power supply;
• a fourth wire coupled to the shared one diffusion layer of the second transistors;
• and
• a fifth wire disposed between the first transistors and the second transistors in the other direction and coupled to shared gate electrodes of the first and second transistors,
• wherein the second layout includes:
• two third transistors having the first conductivity type and one shared diffusion layer;
• two fourth transistors disposed in juxtaposition with the two third transistors in the other direction and having the second conductivity type and one shared diffusion layer;
• a sixth wire coupling together the respective other diffusion layers of the third transistors;
• a seventh wire coupled to the shared one diffusion layer of the third transistors;
• an eighth wire coupling together the respective other diffusion layers of the fourth transistors;
• a ninth wire coupled to the shared one diffusion layer of the fourth transistors;
• and
• a tenth wire disposed between the third transistors and the fourth transistors in the other direction and coupled to shared gate electrodes of the third and fourth transistors,
• wherein the first wire, the second wire, the third wire, and the fourth wire each belonging to the first wiring layer extend in the other direction, and
• wherein the fifth wire, the sixth wire, the seventh wire, the eighth wire, the ninth wire, and the tenth wire each belonging to the first wiring layer extend in the one direction.

A semiconductor device, comprising:

• a function cell designed using a basic cell including a first wiring layer provided over a main surface of a semiconductor substrate and having a predetermined pattern and a second wiring layer provided over the first wiring layer and having a predetermined pattern, the function cell corresponding to the basic cell which is modified to have a predetermined function by changing the pattern of the second wiring layer at a design stage,
• wherein, over the main surface, a plurality of cells including the function cells and the basic cells are provided,
• wherein each of the basic cells has a first layout and a second layout which are disposed in juxtaposition in one direction in a plane parallel with the main surface,
• wherein the first layout includes:
• a first transistor;
• a second transistor disposed in juxtaposition with the first transistor in another direction crossing the one direction in the plane and having a conductivity type different from that of the first transistor;
• a first wire coupling either one diffusion layer of the first transistor to a first power supply;
• a second wire coupled to the other diffusion layer of the first transistor;
• a third wire coupling either one diffusion layer of the second transistor to a second power supply;
• a fourth wire coupled to the other diffusion layer of the second transistor;
• and
• a fifth wire disposed between the first transistor and the second transistor in the other direction and coupled to a shared gate electrode of the first and second transistors,
• wherein the second layout includes:
• a third transistor;
• a fourth transistor disposed in juxtaposition with the third transistor in the other direction and having a conductivity type different from that of the third transistor;
• a sixth wire coupled to either one diffusion layer of the third transistor;
• a seventh wire coupled to the other diffusion layer of the third transistor;
• an eighth wire coupled to either one diffusion layer of the fourth transistor;
• a ninth wire coupled to the other diffusion layer of the fourth transistor;
• and
• a tenth wire disposed between the third transistor and the fourth transistor in the other direction and coupled to a shared gate electrode of the third and fourth transistors,
• wherein the first wire, the second wire, the third wire, and the fourth wire each belonging to the first wiring layer extend in the other direction, and
• wherein the fifth wire, the sixth wire, the seventh wire, the eighth wire, the ninth wire, and the tenth wire each belonging to the first wiring layer extend in the one direction.