System and method for testing and configuration of an FPGA

A method of operating an FPGA comprising the steps of:

• instructing a multiplexer having an output coupled to a programming shift register to select an input receiving configuration values implementing a test protocol,
• instructing a plurality of LUT flip flops to enter a test configuration wherein each said LUT flip flop receives inputs implementing said test protocol, and wherein said LUT flip flops are connected as a shift register,
• clocking said programming shift register to load a first set of elements thereof with LUT Configuration values belonging to said configuration values implementing said test protocol;
• clocking said programming shift register to load a second set of elements of said shift register with routing switch configuration belonging to said configuration values implementing said test protocol,
• instructing said plurality of LUT flip flops to enter an operational configuration wherein each said LUT flip flop receives inputs from the outputs of a plurality of LUTs respectively,
• applying data inputs to said plurality of LUTs,
• clocking said LUT flipflops to sample the outputs of each said LUT into a respective said flipflop, said outputs being responsive to said test protocol and said data inputs,
• instructing said LUT flip flops to enter into a test configuration in which said LUT flip flops are connected in a LUT shift register, and connected as a shift register, and
• clocking said LUT flipflops to read out the values of said LUT shift register comprising said outputs of said LUTs responsive to said test protocol and said data inputs.