Apparatus and method for performing digital infinite impulse filtering
AssigneeNXP B.V.
InventorStefan Quitzk
Life of this patent
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Abstract
Embodiments of An apparatus and method are disclosed. In an embodiment, an apparatus for performing digital infinite impulse response filtering includes a biquad core that includes five multiplier elements, each multiplier element including, a multiplier, a first delay element in series with and after the multiplier, and a second delay element in series with and after the first delay element, and a multiplexer associated with each of the five multiplier elements, each multiplexer configured to provide one of at least two different coefficients to the multiplier of the corresponding multiplier element.
Claims20
An apparatus for performing digital infinite impulse response filtering, the apparatus comprising:
- a biquad core that includes:
- five multiplier elements connected to each other in a biquad core configuration, each multiplier element including:
- a multiplier;
- a first delay element in series with and after the multiplier;
- a second delay element in series with and after the first delay element;
- a multiplexer associated with each of the five multiplier elements, each multiplexer configured to provide one of at least two different coefficients to the multiplier of the corresponding multiplier element.
A method for performing digital infinite impulse response filtering, the method comprising:
- performing multiplication operations in a biquad filter;
- applying two delay elements in series to the results of the multiplication operations;
- and
- switching between two different coefficients on successive multiplication operations.
A method for performing digital infinite impulse response filtering, the method comprising:
- performing first multiplication operations using first coefficients that are provided to multipliers of a biquad core to generate results;
- switching the coefficients that are provided to the multipliers of the biquad core to second coefficients;
- performing second multiplication operations using the second coefficients that are provided to the multipliers of the biquad core to generate results;
- applying a first delay to the results of the first multiplication operations via first delay elements to generate once-delayed results;
- applying a second delay to the once-delayed results via second delay elements to generate twice-delayed results;
- applying the first delay to the results of the second multiplication operations via the first delay element to generate once-delayed results;
- and
- applying the second delay to the once-delayed results via the second delay elements to generate twice-delayed results;
- wherein the switching between coefficients occurs on each clock cycle of a system clock and wherein the first and second delay elements are configured to impart a delay of one clock cycle of the system clock.
Dependencies are inferred from the claim text.