Method and system for a track and hold amplifier with extended dynamic range

A system for communication, the system comprising:

• a track and hold amplifier comprising a first PMOS transistor coupled to a first NMOS transistor, a second PMOS transistor coupled to a second NMOS transistor, a capacitor at a gate terminal of each NMOS and PMOS transistor, and a plurality of switches, the track and hold amplifier being operable to:
• during a tracking mode of the track and hold amplifier:
• operatively couple a differential input signal to each NMOS and PMOS transistor via a first switch coupled to a first capacitor coupled to the gate terminal of the first PMOS transistor and a second capacitor coupled to the gate terminal of the first NMOS transistor, and via a second switch coupled to a third capacitor coupled to the gate terminal of the second PMOS transistor and a fourth capacitor coupled to the gate terminal of the second NMOS transistor;
• operatively couple the gate terminal of the first PMOS transistor to the gate terminal of the second PMOS transistor via a third switch;
• operatively couple the gate terminal of the first NMOS transistor to the gate terminal of the second NMOS transistor via a fourth switch;
• operatively couple a first common mode voltage to the gate terminals of the first and second PMOS transistors;
• and
• operatively couple a second common mode voltage to the gate terminals of the first and second NMOS transistors.

A system for communication, the system comprising:

• a track and hold amplifier comprising a first PMOS transistor coupled to a first NMOS transistor, a second PMOS transistor coupled to a second NMOS transistor, a capacitor at a gate terminal of each NMOS and PMOS transistor, and a plurality of switches, the track and hold amplifier being operable to, during a tracking mode of the track and hold amplifier:
• operatively couple a differential input signal to each NMOS and PMOS transistor via a first switch coupled to a first capacitor coupled to the gate terminal of the first PMOS transistor and a second capacitor coupled to the gate terminal of the first NMOS transistor, and via a second switch coupled to a third capacitor coupled to the gate terminal of the second PMOS transistor and a fourth capacitor coupled to the gate terminal of the second NMOS transistor;
• operatively couple the gate terminal of the first PMOS transistor to the gate terminal of the second PMOS transistor via a third switch;
• operatively couple the gate terminal of the first NMOS transistor to the gate terminal of the second NMOS transistor via a fourth switch;
• and
• short first and second output terminals of the track and hold amplifier together via a fifth switch;
• operatively couple a first common mode voltage from a first switched feedback loop to the gate terminals of the first and second PMOS transistors;
• and
• operatively couple a second common mode voltage from a second switched capacitor feedback loop to the gate terminals of the first and second NMOS transistors.