Controlling a dynamic-stripe-width memory module

A memory control component comprising:

• a data interface to be coupled, via a plurality of data signaling paths, to a respective plurality of memory dies disposed on a memory module;
• control circuitry to:
• transmit to the memory module for storage therein a first configuration value that specifies a memory die quantity N that is permitted to range from a first value corresponding to the quantity of the data signaling paths to at least one value less than the first value;
• transmit a memory read command to the memory module to enable therein, in accordance with the first configuration value, a quantity N of the memory dies to output read data, the read data constituted by a predetermined number of bytes that is independent of the quantity N of the memory dies such that the portion of the read data output by each memory die of the quantity N of the memory dies is inversely proportional to N;
• and
• enable reception within the data interface of the read data output by the quantity N of the memory dies via a respective quantity N of the data signaling paths.

A memory control component comprising:

• a data interface to be coupled, via a plurality of data signaling paths, to a respective plurality of memory dies disposed on a memory module
• means for transmitting to the memory module:
• a first configuration value, for storage within the memory module, that specifies a memory die quantity N that is permitted to range from a first value corresponding to the quantity of the data signaling paths to at least one value less than the first value;
• and
• a memory read command to enable, in accordance with the first configuration value, a quantity N of the memory dies to output read data, the read data constituted by a predetermined number of bytes that is independent of the quantity N of the memory dies such that the portion of the read data output by each memory die of the quantity N of the memory dies is inversely proportional to N;
• and
• means for receiving the read data output by the quantity N of the memory dies via a respective quantity N of the data signaling paths.