Amplifier circuit devices and methods
AssigneeArm Limited
InventorsEl Mehdi Boujamaa, Cyrille Nicolas Dray
Life of this patent
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Abstract
In a particular implementation, an apparatus including first and second bias circuits and an inner amplifier provides sense amplifier offset cancellation. The inner amplifier includes: first and second current generators configured to replicate respective first and second currents from the first and second bias circuits, first and second transistors configured to transform the first and second currents into voltage samples, and first and second capacitors configured to store the voltage samples. In a sampling phase, a sampling of the first and second currents may be performed in the inner amplifier, and further, in an amplification phase, an amplification of the stored voltage samples may also be performed in the inner amplifier.
Claims20
An amplifier circuit comprising:
- first and second bias circuits;
- and
- an inner amplifier coupled to the first and second bias circuits comprising:
- first and second current generators configured to replicate respective first and second currents from the first and second bias circuits,
- first and second transistors configured to transform the first and second currents into voltage samples, and
- first and second capacitors configured to store the voltage samples,
- wherein in a sampling phase, a sampling of the first and second currents is performed in the inner amplifier, and wherein in an amplification phase, an amplification of the stored voltage samples is performed in the inner amplifier.
A method comprising:
- in a sampling phase:
- receiving, in an amplifier circuit, a first reference current and a bit current on respective first and second bias circuits;
- replicating the first reference current and the bit current from the first and second bias circuits to first and second current generators in an inner amplifier of the amplifier circuit;
- converting, at respective first and second transistors of the inner amplifier, the reference current into a first voltage sample and the bit current into a second voltage sample;
- and
- storing, at respective first and second capacitors of the inner amplifier, the first and second voltage samples;
- and
- in an amplification phase:
- receiving, in the amplifier circuit, the bit current and a second reference current on the respective first and second bias circuits;
- replicating the bit current and the second reference current from the first and second bias circuits to the first and second current generators in an inner amplifier of the amplifier circuit;
- and
- determining, at a node between the first current generator and first transistor device, and at a node between the second current generator and second transistor device, first and second output voltages.
An amplifier circuit comprising:
- first and second bias circuits;
- an inner amplifier coupled to the first and second bias circuits, wherein the inner amplifier is configured to determine if a stored voltage sample corresponding to a bit memory element indicates a high resistive state or a low resistive state, wherein the inner amplifier comprises:
- first and second current generators configured to replicate respective first and second currents from the first and second bias circuits;
- first and second transistors configured to transform the first and second currents into voltage samples;
- and
- first and second capacitors configured to store the voltage samples.
Dependencies are inferred from the claim text.