Private memory access for a reconfigurable parallel processor using a plurality of chained memory ports
AssigneeAzurEngine Technologies Zhuhai Inc.
InventorsYuan Li, Jianbin Zhu
Life of this patent
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Abstract
Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) and a plurality of memory ports (MPs) for the plurality of PEs to access a memory unit. Each PE may have a plurality of arithmetic logic units (ALUs) that are configured to execute a same instruction in parallel threads. Each of the plurality of MPs may comprise an address calculation unit configured to generate respective memory addresses for each thread to access a different memory bank in the memory unit.
Claims20
A processor, comprising:
- a plurality of processing elements (PEs) each having a plurality of arithmetic logic units (ALUs) that are configured to execute a same instruction in parallel threads;
- and
- a plurality of memory ports (MPs) chained to form a data routing bus and coupled to the plurality of PEs for the plurality of PEs to access a memory unit commonly accessible to the plurality of PEs, each of the plurality of MPs comprising an address calculation unit configured to generate respective memory addresses for each concurrent thread in one PE of the plurality of PEs to access a different memory bank in the memory unit.
A method, comprising:
- generating a plurality of memory addresses by an address calculation unit in a memory port (MP) of a plurality of memory ports, wherein the plurality of memory ports are chained to form a data routing bus and coupled to a plurality of processing elements (PEs) for the plurality of PEs to access a memory unit commonly accessible to the plurality of PEs, wherein each PE has a plurality of arithmetic logic units (ALUs) that are configured to execute a same instruction in parallel threads, and the plurality of memory addresses are generated for a PE of the plurality of PEs;
- and
- accessing a plurality of memory banks in the memory unit using the plurality of memory addresses with each concurrent thread in the PE accessing a different memory bank in the memory unit.
A method, comprising:
- generating a plurality of memory addresses in an external memory unit by an address calculation unit in a memory port (MP) of a chain of memory ports (MPs) that form a data routing bus, wherein the memory port provides access to the external memory unit for a processing element (PE) having a plurality of arithmetic logic units (ALUs) configured to execute a same instruction in parallel threads;
- and
- accessing a plurality of memory banks in the external memory unit using the plurality of memory addresses with each thread accessing a different memory bank in the external memory unit.
Dependencies are inferred from the claim text.