MRAM sense amplifier with second stage offset cancellation

A magnetoresistive random access memory (MRAM) system, comprising:

• a plurality of MRAM data cells;
• and
• a sense amplifier circuit for sensing a data state of a data cell of the plurality of MRAM data cells during a read cycle, the sense amplifier circuit comprising:
• a first stage, comprising first circuitry configured to output a reference voltage and a data voltage relating to the data state of the data cell;
• and
• a second stage, comprising second circuitry configured to amplify a difference between the reference voltage and the data voltage, the second circuitry comprising:
• a plurality of inverters;
• and
• a plurality of capacitors, wherein
• the read cycle comprises a compensation phase and wherein during the compensation phase the second circuitry is configured to store, at the capacitors, a voltage difference caused by a device mismatch of the inverters, and
• wherein after the compensation phase the second circuitry is configured to amplify the difference between the reference voltage and the data voltage, and to compensate for the device mismatch using the stored voltage difference at the capacitors.

A method of reading data from a magnetoresistive random access memory (MRAM) system, comprising:

• generating a reference voltage and a data voltage relating to a data state of a data cell in the MRAM system by performing a read of the data cell during a read cycle, using a first stage of a sense amplifier circuit;
• amplifying a difference between the reference voltage and the data voltage, during the read cycle, using a second stage of the sense amplifier circuit, the second stage comprising:
• a plurality of inverters;
• and
• a plurality of capacitors;
• wherein the read cycle comprises a compensation phase and wherein during the compensation phase the second stage is configured to store, at the capacitors, a voltage difference caused by a device mismatch of the inverters, and
• wherein after the compensation phase the second stage is configured to amplify the difference between the reference voltage and the data voltage, and to compensate for the device mismatch using the stored voltage difference at the capacitors.