Trimming MRAM sense amp with offset cancellation

A magnetoresistive random access memory (MRAM) system, comprising:

• a plurality of MRAM data cells;
• and
• a sense amplifier circuit for sensing a data state of a data cell of the plurality of MRAM data cells, the sense amplifier circuit comprising:
• a first leg comprising a first transistor and a second leg comprising a second transistor, wherein the sense amplifier circuit is configured to perform a two-phase read comprising:
• a first phase in which the first transistor is coupled to a reference resistance circuitry and the second transistor is coupled to a data resistance circuitry, and
• a second phase in which the first transistor is coupled to the data resistance circuitry and the second transistor is coupled to the reference resistance circuitry;
• a reference trim circuitry coupled to the reference resistance circuitry and a data trim circuitry coupled to the data resistance circuitry, the reference trim circuitry and data trim circuitry configured to correct for device mismatch errors relating to the two-phase read of the sense amplifier circuit;
• and
• a comparator circuit configured to output the data state of the data cell based on input of a first voltage related to a reference resistance and a second voltage related to a data resistance.

A method of reading data from a magnetoresistive random access memory (MRAM) system, comprising:

• performing a two phase read of a data state of a data cell using a sense amplifier circuit, the sense amplifier circuit comprising:
• a first leg comprising a first transistor;
• a second leg comprising a second transistor;
• a reference trim circuitry;
• a data trim circuitry;
• and
• a comparator circuit;
• wherein during a first phase of the two phase read the first transistor is coupled to a reference resistance circuitry and the second transistor is coupled to a data resistance circuitry,
• wherein during a second phase of the two phase read the first transistor is coupled to the data resistance circuitry and the second transistor is coupled to the reference resistance circuitry,
• wherein the reference trim circuitry is coupled to the reference resistance circuitry and the data trim circuitry is coupled to the data resistance circuitry, the reference trim circuitry and data trim circuitry configured to correct for device mismatch errors relating to the two phase read of the sense amplifier circuit, and
• wherein the comparator circuit is configured to output the data state of the data cell based on input of a first voltage related to a reference resistance and a second voltage related to a data resistance.