Reducing post-read disturb in a nonvolatile memory device

A method comprising:

• performing a read operation to read data stored in a block of memory cells arranged in NAND strings;
• subsequent to the read operation, discharging local word lines of the block to substantially zero volts;
• isolating channels of the NAND strings;
• isolating the local word lines of the block from global word lines;
• and
• subsequently applying a low positive voltage on the global word lines while the local word lines remain isolated from the global word lines.

An apparatus, comprising:

• a plurality of NAND strings in a block, each NAND string comprising a source-end select gate transistor, a drain-end select gate transistor, and memory cells between the source-end select gate transistor and the drain-end select gate transistor;
• local word lines connected to cells in the plurality of NAND strings, the local word lines selectively coupled to global word lines by block select transistors;
• select lines connected to select gate transistors in the plurality of NAND strings;
• and
• means for discharging the local word lines to substantially zero volts after a read operation and subsequently applying a low positive voltage on the global word lines while the global word lines are isolated from the local word lines.