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US 10,725,777 B2Granted
Computational memory cell and processing array device using memory cells
AssigneeGSI Technology, Inc.
InventorsLee-Lean Shu, Chao-Hung Chang, Avidan Akerib
Life of this patent
Estimating the term…
Abstract
A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.
Claims19
A processing array, comprising:
- a plurality of memory cells arranged in an array, wherein each memory cell has a storage cell, wherein the storage cell of each memory cell further comprises a first inverter having an input and an output and a second inverter having an input coupled to the output of the first inverter and an output coupled to the input of the first inverter, a first access transistor coupled to the input of the first inverter and the output of the second inverter and a gate of the first access transistor coupled to a write bit line and a second access transistor coupled to the output of the first inverter and the input of the second inverter and a gate of the second access transistor coupled to a complementary write bit line;
- a word line generator that is coupled to a read word line signal and a write word line signal for each memory cell in the array;
- a plurality of bit line read and write logic circuits that are coupled to the read bit line, write bit line and a complementary write bit line of each memory cell;
- a write port with the write word line coupled to a gate of a write port transistor, a drain of the write port transistor coupled to a source of the first access transistor and a source of the second access transistor;
- each memory cell being coupled to a write word line and a read word line whose signals are generated by the word line generator and also being coupled to a read bit line, a write bit line and a complementary write bit line that are sensed by one of the plurality of bit line read and write logic circuits;
- each memory cell having an isolation circuit that isolates a data signal representing a piece of data stored in the storage cell of the memory cell from the read bit line;
- wherein two or more of the memory cells are coupled to at least one read bit line and activated to perform a computational operation;
- and
- wherein the read bit line is capable of being used to provide read access to the storage cell data.
6 more elements
A processing array, comprising:
- a plurality of memory cells arranged in an array, wherein each memory cell has a storage cell, wherein the storage cell of each memory cell further comprises a first inverter having an input and an output and a second inverter having an input coupled to the output of the first inverter and an output coupled to the input of the first inverter, a first access transistor coupled to the input of the first inverter and the output of the second inverter and a gate coupled to a write bit line and a second access transistor coupled to the output of the first inverter and the input of the second inverter and a gate coupled to a complementary write bit line;
- a word line generator that is coupled to a read word line signal and a write word line signal for each memory cell in the array;
- a plurality of bit line read and write logic circuits that are coupled to the read bit line, write bit line and a complementary write bit line of each memory cell;
- a write port with the write word line coupled to a gate of a first write port transistor and a gate of a second write port transistor, a drain of the first write port transistor coupled to a source of the first access transistor and a drain of the second write port transistor coupled to a source of the second access transistor;
- each memory cell being coupled to a write word line and a read word line whose signals are generated by the word line generator and also being coupled to a read bit line, a write bit line and a complementary write bit line that are sensed by one of the plurality of bit line read and write logic circuits;
- each memory cell having an isolation circuit that isolates a data signal representing a piece of data stored in the storage cell of the memory cell from the read bit line;
- wherein two or more of the memory cells are coupled to at least one read bit line and activated to perform a computational operation;
- and
- wherein the read bit line is capable of being used to provide read access to the storage cell data.
6 more elements
A processing array, comprising:
- a plurality of memory cells arranged in an array, wherein each memory cell has a storage cell;
- a word line generator that is coupled to a read word line signal and a write word line signal for each memory cell in the array;
- a plurality of bit line read and write logic circuits that are coupled to the read bit line, write bit line and a complementary write bit line of each memory cell;
- each memory cell being coupled to a write word line and a read word line whose signals are generated by the word line generator and also being coupled to a read bit line, a write bit line and a complementary write bit line that are sensed by one of the plurality of bit line read and write logic circuits;
- each memory cell having an isolation circuit that isolates a data signal representing a piece of data stored in the storage cell of the memory cell from the read bit line;
- wherein two or more of the memory cells are coupled to at least one read bit line and activated to perform a computational operation;
- wherein the read bit line is capable of being used to provide read access to the storage cell data;
- and
- wherein the processing array is capable of performing parallel shifting operation.
6 more elements
A processing array, comprising:
- a plurality of memory cells arranged in an array, wherein each memory cell has a storage cell;
- a word line generator that is coupled to a read word line signal and a write word line signal for each memory cell in the array;
- a plurality of bit line read and write logic circuits that are coupled to the read bit line, write bit line and a complementary write bit line of each memory cell;
- each memory cell being coupled to a write word line and a read word line whose signals are generated by the word line generator and also being coupled to a read bit line, a write bit line and a complementary write bit line that are sensed by one of the plurality of bit line read and write logic circuits;
- each memory cell having an isolation circuit that isolates a data signal representing a piece of data stored in the storage cell of the memory cell from the read bit line;
- wherein two or more of the memory cells are coupled to at least one read bit line and activated to perform a computational operation;
- wherein the read bit line is capable of being used to provide read access to the storage cell data;
- and
- wherein the processing array is capable of performing a search operation.
6 more elements
A processing array, comprising:
- at least one read bit line;
- at least two memory cells connected to the at least one read bit line, each memory cell having a storage cell and an isolation circuit that buffers the storage cell from signals on the at least one read bit line;
- a write bit line connected to the at least two memory cells wherein data is written into the storage cell of one or more of the at least two memory cells;
- a write port device that buffers the storage cell of each of the plurality of memory cells so that writing of data into any number of storage cells is performed;
- wherein the at least two memory cells connected to the at least one read bit line perform a logic operation on the at least one read bit line by turning on the at least two memory cells connected to the at least one read bit line and performing a read of the at least one bit line;
- and
- wherein the read bit line is capable of being used to provide read access to the storage cell data.
4 more elements
A processing array, comprising:
- at least one read bit line;
- at least two memory cells connected to the at least one read bit line, each memory cell having a storage cell and an isolation circuit that buffers the storage cell from signals on the at least one read bit line;
- wherein the at least two memory cells connected to the at least one read bit line perform a logic operation on the at least one read bit line by turning on the at least two memory cells connected to the at least one read bit line;
- wherein the read bit line is capable of being used to provide read access to the storage cell data;
- and
- wherein the processing array is capable of performing parallel shifting operation.
3 more elements
A processing array, comprising:
- at least one read bit line;
- at least two memory cells connected to the at least one read bit line, each memory cell having a storage cell and an isolation circuit that buffers the storage cell from signals on the at least one read bit line;
- wherein the at least two memory cells connected to the at least one read bit line perform a logic operation on the at least one read bit line by turning on the at least two memory cells connected to the at least one read bit line;
- wherein the read bit line is capable of being used to provide read access to the storage cell data;
- and
- wherein the processing array is capable of performing a search operation.
3 more elements
Dependencies are inferred from the claim text.